PPC: [wasm-simd] Implement Load Transform on PPC LE
Change-Id: I3bb6a6822dea5ce6aa3e12f3137861a2f93bbb68 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2560604 Reviewed-by: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#71416}
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src
codegen/ppc
compiler/backend/ppc
@ -2373,6 +2373,8 @@ using Instr = uint32_t;
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V(vbpermq, VBPERMQ, 0x1000054C)
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#define PPC_VX_OPCODE_C_FORM_LIST(V) \
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/* Vector Unpack High Signed Word */ \
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V(vupkhsw, VUPKHSW, 0x1000064E) \
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/* Vector Unpack Low Signed Halfword */ \
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V(vupklsh, VUPKLSH, 0x100002CE) \
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/* Vector Unpack High Signed Halfword */ \
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@ -2547,8 +2549,6 @@ using Instr = uint32_t;
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V(vsumsws, VSUMSWS, 0x10000788) \
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/* Vector Unpack High Pixel */ \
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V(vupkhpx, VUPKHPX, 0x1000034E) \
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/* Vector Unpack High Signed Word */ \
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V(vupkhsw, VUPKHSW, 0x1000064E) \
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/* Vector Unpack Low Pixel */ \
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V(vupklpx, VUPKLPX, 0x100003CE) \
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/* Vector Unpack Low Signed Word */ \
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@ -3464,6 +3464,107 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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__ vsel(dst, src0, src1, kScratchDoubleReg);
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break;
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}
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#define ASSEMBLE_LOAD_TRANSFORM(scratch) \
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AddressingMode mode = kMode_None; \
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MemOperand operand = i.MemoryOperand(&mode); \
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DCHECK_EQ(mode, kMode_MRR); \
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__ lxvd(scratch, operand);
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case kPPC_S128Load8Splat: {
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vspltb(dst, kScratchDoubleReg, Operand(7));
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break;
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}
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case kPPC_S128Load16Splat: {
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vsplth(dst, kScratchDoubleReg, Operand(3));
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break;
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}
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case kPPC_S128Load32Splat: {
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vspltw(dst, kScratchDoubleReg, Operand(1));
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break;
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}
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case kPPC_S128Load64Splat: {
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constexpr int lane_width_in_bytes = 8;
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(dst)
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__ vinsertd(dst, dst, Operand(1 * lane_width_in_bytes));
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break;
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}
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case kPPC_S128Load8x8S: {
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vupkhsb(dst, kScratchDoubleReg);
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break;
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}
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case kPPC_S128Load8x8U: {
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vupkhsb(dst, kScratchDoubleReg);
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// Zero extend.
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__ li(ip, Operand(0xFF));
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__ mtvsrd(kScratchDoubleReg, ip);
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__ vsplth(kScratchDoubleReg, kScratchDoubleReg, Operand(3));
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__ vand(dst, kScratchDoubleReg, dst);
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break;
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}
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case kPPC_S128Load16x4S: {
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vupkhsh(dst, kScratchDoubleReg);
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break;
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}
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case kPPC_S128Load16x4U: {
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vupkhsh(dst, kScratchDoubleReg);
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// Zero extend.
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__ mov(ip, Operand(0xFFFF));
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__ mtvsrd(kScratchDoubleReg, ip);
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__ vspltw(kScratchDoubleReg, kScratchDoubleReg, Operand(1));
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__ vand(dst, kScratchDoubleReg, dst);
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break;
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}
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case kPPC_S128Load32x2S: {
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vupkhsw(dst, kScratchDoubleReg);
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break;
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}
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case kPPC_S128Load32x2U: {
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constexpr int lane_width_in_bytes = 8;
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vupkhsw(dst, kScratchDoubleReg);
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// Zero extend.
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__ mov(ip, Operand(0xFFFFFFFF));
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__ mtvsrd(kScratchDoubleReg, ip);
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__ vinsertd(kScratchDoubleReg, kScratchDoubleReg,
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Operand(1 * lane_width_in_bytes));
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__ vand(dst, kScratchDoubleReg, dst);
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break;
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}
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case kPPC_S128Load32Zero: {
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constexpr int lane_width_in_bytes = 4;
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vxor(dst, dst, dst);
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__ vinsertw(dst, kScratchDoubleReg, Operand(3 * lane_width_in_bytes));
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break;
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}
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case kPPC_S128Load64Zero: {
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constexpr int lane_width_in_bytes = 8;
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Simd128Register dst = i.OutputSimd128Register();
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ASSEMBLE_LOAD_TRANSFORM(kScratchDoubleReg)
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__ vxor(dst, dst, dst);
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__ vinsertd(dst, kScratchDoubleReg, Operand(1 * lane_width_in_bytes));
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break;
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}
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#undef ASSEMBLE_LOAD_TRANSFORM
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case kPPC_StoreCompressTagged: {
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ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
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break;
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@ -379,6 +379,18 @@ namespace compiler {
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V(PPC_S128Not) \
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V(PPC_S128Select) \
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V(PPC_S128AndNot) \
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V(PPC_S128Load8Splat) \
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V(PPC_S128Load16Splat) \
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V(PPC_S128Load32Splat) \
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V(PPC_S128Load64Splat) \
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V(PPC_S128Load8x8S) \
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V(PPC_S128Load8x8U) \
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V(PPC_S128Load16x4S) \
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V(PPC_S128Load16x4U) \
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V(PPC_S128Load32x2S) \
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V(PPC_S128Load32x2U) \
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V(PPC_S128Load32Zero) \
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V(PPC_S128Load64Zero) \
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V(PPC_StoreCompressTagged) \
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V(PPC_LoadDecompressTaggedSigned) \
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V(PPC_LoadDecompressTaggedPointer) \
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@ -322,6 +322,18 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_LoadDecompressTaggedSigned:
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case kPPC_LoadDecompressTaggedPointer:
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case kPPC_LoadDecompressAnyTagged:
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case kPPC_S128Load8Splat:
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case kPPC_S128Load16Splat:
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case kPPC_S128Load32Splat:
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case kPPC_S128Load64Splat:
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case kPPC_S128Load8x8S:
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case kPPC_S128Load8x8U:
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case kPPC_S128Load16x4S:
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case kPPC_S128Load16x4U:
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case kPPC_S128Load32x2S:
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case kPPC_S128Load32x2U:
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case kPPC_S128Load32Zero:
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case kPPC_S128Load64Zero:
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return kIsLoadOperation;
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case kPPC_StoreWord8:
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@ -2483,7 +2483,56 @@ void InstructionSelector::EmitPrepareResults(
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}
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}
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void InstructionSelector::VisitLoadTransform(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitLoadTransform(Node* node) {
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LoadTransformParameters params = LoadTransformParametersOf(node->op());
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PPCOperandGenerator g(this);
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Node* base = node->InputAt(0);
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Node* index = node->InputAt(1);
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ArchOpcode opcode;
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switch (params.transformation) {
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case LoadTransformation::kS128Load8Splat:
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opcode = kPPC_S128Load8Splat;
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break;
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case LoadTransformation::kS128Load16Splat:
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opcode = kPPC_S128Load16Splat;
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break;
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case LoadTransformation::kS128Load32Splat:
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opcode = kPPC_S128Load32Splat;
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break;
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case LoadTransformation::kS128Load64Splat:
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opcode = kPPC_S128Load64Splat;
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break;
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case LoadTransformation::kS128Load8x8S:
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opcode = kPPC_S128Load8x8S;
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break;
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case LoadTransformation::kS128Load8x8U:
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opcode = kPPC_S128Load8x8U;
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break;
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case LoadTransformation::kS128Load16x4S:
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opcode = kPPC_S128Load16x4S;
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break;
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case LoadTransformation::kS128Load16x4U:
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opcode = kPPC_S128Load16x4U;
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break;
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case LoadTransformation::kS128Load32x2S:
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opcode = kPPC_S128Load32x2S;
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break;
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case LoadTransformation::kS128Load32x2U:
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opcode = kPPC_S128Load32x2U;
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break;
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case LoadTransformation::kS128Load32Zero:
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opcode = kPPC_S128Load32Zero;
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break;
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case LoadTransformation::kS128Load64Zero:
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opcode = kPPC_S128Load64Zero;
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break;
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default:
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UNREACHABLE();
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}
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Emit(opcode | AddressingModeField::encode(kMode_MRR),
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g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(index));
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}
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// static
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MachineOperatorBuilder::Flags
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