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[turbofan] Added the RoundInt64ToFloat64 instruction to TurboFan.

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Review URL: https://codereview.chromium.org/1424333002

Cr-Commit-Position: refs/heads/master@{#31752}
This commit is contained in:
ahaas 2015-11-03 07:46:00 -08:00 committed by Commit bot
parent b5d0e31582
commit 870e908d88
20 changed files with 81 additions and 2 deletions
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3
src/compiler/arm64/code-generator-arm64.cc
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@ -912,6 +912,9 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
case kArm64Int32ToFloat64:
__ Scvtf(i.OutputDoubleRegister(), i.InputRegister32(0));
break;
case kArm64Int64ToFloat64:
__ Scvtf(i.OutputDoubleRegister(), i.InputRegister64(0));
break;
case kArm64Uint32ToFloat64:
__ Ucvtf(i.OutputDoubleRegister(), i.InputRegister32(0));
break;

1
src/compiler/arm64/instruction-codes-arm64.h
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@ -107,6 +107,7 @@ namespace compiler {
V(Arm64Float64ToInt32) \
V(Arm64Float64ToUint32) \
V(Arm64Int32ToFloat64) \
V(Arm64Int64ToFloat64) \
V(Arm64Uint32ToFloat64) \
V(Arm64Float64ExtractLowWord32) \
V(Arm64Float64ExtractHighWord32) \

5
src/compiler/arm64/instruction-selector-arm64.cc
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@ -1282,6 +1282,11 @@ void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) {
}
void InstructionSelector::VisitRoundInt64ToFloat64(Node* node) {
VisitRR(this, kArm64Int64ToFloat64, node);
}
void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) {
VisitRR(this, kArm64Float64ExtractLowWord32, node);
}

7
src/compiler/instruction-selector.cc
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@ -710,6 +710,8 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsWord32(node), VisitTruncateFloat64ToInt32(node);
case IrOpcode::kTruncateInt64ToInt32:
return MarkAsWord32(node), VisitTruncateInt64ToInt32(node);
case IrOpcode::kRoundInt64ToFloat64:
return MarkAsFloat64(node), VisitRoundInt64ToFloat64(node);
case IrOpcode::kBitcastFloat32ToInt32:
return MarkAsWord32(node), VisitBitcastFloat32ToInt32(node);
case IrOpcode::kBitcastFloat64ToInt64:
@ -924,6 +926,11 @@ void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) {
}
void InstructionSelector::VisitRoundInt64ToFloat64(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitBitcastFloat64ToInt64(Node* node) {
UNIMPLEMENTED();
}

1
src/compiler/machine-operator.cc
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@ -131,6 +131,7 @@ CheckedStoreRepresentation CheckedStoreRepresentationOf(Operator const* op) {
V(ChangeFloat64ToInt32, Operator::kNoProperties, 1, 0, 1) \
V(ChangeFloat64ToUint32, Operator::kNoProperties, 1, 0, 1) \
V(ChangeInt32ToFloat64, Operator::kNoProperties, 1, 0, 1) \
V(RoundInt64ToFloat64, Operator::kNoProperties, 1, 0, 1) \
V(ChangeInt32ToInt64, Operator::kNoProperties, 1, 0, 1) \
V(ChangeUint32ToFloat64, Operator::kNoProperties, 1, 0, 1) \
V(ChangeUint32ToUint64, Operator::kNoProperties, 1, 0, 1) \

5
src/compiler/machine-operator.h
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@ -193,11 +193,12 @@ class MachineOperatorBuilder final : public ZoneObject {
const Operator* ChangeUint32ToFloat64();
const Operator* ChangeUint32ToUint64();
// These operators truncate numbers, both changing the representation of
// the number and mapping multiple input values onto the same output value.
// These operators truncate or round numbers, both changing the representation
// of the number and mapping multiple input values onto the same output value.
const Operator* TruncateFloat64ToFloat32();
const Operator* TruncateFloat64ToInt32(TruncationMode);
const Operator* TruncateInt64ToInt32();
const Operator* RoundInt64ToFloat64();
// These operators reinterpret the bits of a floating point number as an
// integer and vice versa.

6
src/compiler/mips64/code-generator-mips64.cc
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@ -798,6 +798,12 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ cvt_d_w(i.OutputDoubleRegister(), scratch);
break;
}
case kMips64CvtDL: {
FPURegister scratch = kScratchDoubleReg;
__ dmtc1(i.InputRegister(0), scratch);
__ cvt_d_l(i.OutputDoubleRegister(), scratch);
break;
}
case kMips64CvtDUw: {
FPURegister scratch = kScratchDoubleReg;
__ Cvt_d_uw(i.OutputDoubleRegister(), i.InputRegister(0), scratch);

1
src/compiler/mips64/instruction-codes-mips64.h
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@ -73,6 +73,7 @@ namespace compiler {
V(Mips64TruncWD) \
V(Mips64TruncUwD) \
V(Mips64CvtDW) \
V(Mips64CvtDL) \
V(Mips64CvtDUw) \
V(Mips64Lb) \
V(Mips64Lbu) \

5
src/compiler/mips64/instruction-selector-mips64.cc
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@ -584,6 +584,11 @@ void InstructionSelector::VisitTruncateFloat64ToInt32(Node* node) {
}
void InstructionSelector::VisitRoundInt64ToFloat64(Node* node) {
VisitRR(this, kMips64CvtDL, node);
}
void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) {
VisitRR(this, kMips64Float64ExtractLowWord32, node);
}

1
src/compiler/opcodes.h
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@ -268,6 +268,7 @@
V(TruncateFloat64ToFloat32) \
V(TruncateFloat64ToInt32) \
V(TruncateInt64ToInt32) \
V(RoundInt64ToFloat64) \
V(BitcastFloat32ToInt32) \
V(BitcastFloat64ToInt64) \
V(BitcastInt32ToFloat32) \

3
src/compiler/raw-machine-assembler.h
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@ -457,6 +457,9 @@ class RawMachineAssembler {
Node* TruncateInt64ToInt32(Node* a) {
return AddNode(machine()->TruncateInt64ToInt32(), a);
}
Node* RoundInt64ToFloat64(Node* a) {
return AddNode(machine()->RoundInt64ToFloat64(), a);
}
Node* BitcastFloat32ToInt32(Node* a) {
return AddNode(machine()->BitcastFloat32ToInt32(), a);
}

5
src/compiler/typer.cc
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@ -2017,6 +2017,11 @@ Type* Typer::Visitor::TypeTruncateInt64ToInt32(Node* node) {
}
Type* Typer::Visitor::TypeRoundInt64ToFloat64(Node* node) {
return Type::Intersect(Type::PlainNumber(), Type::UntaggedFloat64(), zone());
}
Type* Typer::Visitor::TypeBitcastFloat32ToInt32(Node* node) {
return Type::Number();
}

1
src/compiler/verifier.cc
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@ -878,6 +878,7 @@ void Verifier::Visitor::Check(Node* node) {
case IrOpcode::kFloat64LessThan:
case IrOpcode::kFloat64LessThanOrEqual:
case IrOpcode::kTruncateInt64ToInt32:
case IrOpcode::kRoundInt64ToFloat64:
case IrOpcode::kTruncateFloat64ToFloat32:
case IrOpcode::kTruncateFloat64ToInt32:
case IrOpcode::kBitcastFloat32ToInt32:

7
src/compiler/x64/code-generator-x64.cc
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@ -939,6 +939,13 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ Cvtlsi2sd(i.OutputDoubleRegister(), i.InputOperand(0));
}
break;
case kSSEInt64ToFloat64:
if (instr->InputAt(0)->IsRegister()) {
__ Cvtqsi2sd(i.OutputDoubleRegister(), i.InputRegister(0));
} else {
__ Cvtqsi2sd(i.OutputDoubleRegister(), i.InputOperand(0));
}
break;
case kSSEUint32ToFloat64:
if (instr->InputAt(0)->IsRegister()) {
__ movl(kScratchRegister, i.InputRegister(0));

1
src/compiler/x64/instruction-codes-x64.h
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@ -76,6 +76,7 @@ namespace compiler {
V(SSEFloat64ToInt32) \
V(SSEFloat64ToUint32) \
V(SSEInt32ToFloat64) \
V(SSEInt64ToFloat64) \
V(SSEUint32ToFloat64) \
V(SSEFloat64ExtractLowWord32) \
V(SSEFloat64ExtractHighWord32) \

6
src/compiler/x64/instruction-selector-x64.cc
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@ -918,6 +918,12 @@ void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) {
}
void InstructionSelector::VisitRoundInt64ToFloat64(Node* node) {
X64OperandGenerator g(this);
Emit(kSSEInt64ToFloat64, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}
void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) {
X64OperandGenerator g(this);
Emit(kX64BitcastFI, g.DefineAsRegister(node), g.Use(node->InputAt(0)));

3
src/x64/assembler-x64.h
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@ -1363,6 +1363,9 @@ class Assembler : public AssemblerBase {
XMMRegister isrc2 = {src2.code()};
vsd(0x2a, dst, src1, isrc2, kF2, k0F, kW1);
}
void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
vsd(0x2a, dst, src1, src2, kF2, k0F, kW1);
}
void vcvttsd2si(Register dst, XMMRegister src) {
XMMRegister idst = {dst.code()};
vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0);

12
src/x64/macro-assembler-x64.cc
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@ -863,6 +863,18 @@ void MacroAssembler::Cvtqsi2sd(XMMRegister dst, Register src) {
}
void MacroAssembler::Cvtqsi2sd(XMMRegister dst, const Operand& src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vxorpd(dst, dst, dst);
vcvtqsi2sd(dst, dst, src);
} else {
xorpd(dst, dst);
cvtqsi2sd(dst, src);
}
}
void MacroAssembler::Cvtsd2si(Register dst, XMMRegister src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);

1
src/x64/macro-assembler-x64.h
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@ -817,6 +817,7 @@ class MacroAssembler: public Assembler {
void Cvtlsi2sd(XMMRegister dst, Register src);
void Cvtlsi2sd(XMMRegister dst, const Operand& src);
void Cvtqsi2sd(XMMRegister dst, Register src);
void Cvtqsi2sd(XMMRegister dst, const Operand& src);
void Cvtsd2si(Register dst, XMMRegister src);

9
test/cctest/compiler/test-run-machops.cc
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@ -5384,6 +5384,15 @@ TEST(RunBitcastFloat64ToInt64) {
CHECK_EQ(expected, output);
}
}
TEST(RunRoundInt64ToFloat64) {
BufferedRawMachineAssemblerTester<double> m(kMachInt64);
m.Return(m.RoundInt64ToFloat64(m.Parameter(0)));
FOR_INT64_INPUTS(i) { CHECK_EQ(static_cast<double>(*i), m.Call(*i)); }
}
#endif