S390: Implemented ALCR in S390 simulator.
This CL implements the ALCR, add logical 32-bit integer with carry, instruction in the s390 simulator. Some 64-bit operations in the 4-byte arithmetic section of the s390 simulator have been refactored into a separate function to stay below 500 lines. R=michael_dawson@ca.ibm.com,jyan@ca.ibm.com,mbrandy@us.ibm.com,joransiu@ca.ibm.com, BUG= Review URL: https://codereview.chromium.org/1846673003 Cr-Commit-Position: refs/heads/master@{#35184}
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@ -1822,8 +1822,7 @@ bool Simulator::DecodeTwoByte(Instruction* instr) {
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UNREACHABLE();
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}
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set_low_register(r1, alu_out);
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SetS390ConditionCode<uint32_t>(alu_out, 0);
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SetS390OverflowCode(isOF);
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SetS390ConditionCodeCarry<uint32_t>(alu_out, isOF);
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break;
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}
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case LNR: {
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@ -2457,13 +2456,9 @@ bool Simulator::DecodeFourByte(Instruction* instr) {
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return true;
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}
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/**
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* Decodes and simulates four byte arithmetic instructions
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*/
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bool Simulator::DecodeFourByteArithmetic(Instruction* instr) {
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bool Simulator::DecodeFourByteArithmetic64Bit(Instruction* instr) {
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Opcode op = instr->S390OpcodeValue();
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// Pre-cast instruction to various types
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RRFInstruction* rrfInst = reinterpret_cast<RRFInstruction*>(instr);
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RREInstruction* rreInst = reinterpret_cast<RREInstruction*>(instr);
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@ -2537,6 +2532,112 @@ bool Simulator::DecodeFourByteArithmetic(Instruction* instr) {
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set_register(r1, r1_val);
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break;
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}
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case AGRK:
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case SGRK:
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case NGRK:
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case OGRK:
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case XGRK: {
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// 64-bit Non-clobbering arithmetics / bitwise ops.
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int r1 = rrfInst->R1Value();
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int r2 = rrfInst->R2Value();
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int r3 = rrfInst->R3Value();
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int64_t r2_val = get_register(r2);
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int64_t r3_val = get_register(r3);
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if (AGRK == op) {
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bool isOF = CheckOverflowForIntAdd(r2_val, r3_val, int64_t);
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SetS390ConditionCode<int64_t>(r2_val + r3_val, 0);
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SetS390OverflowCode(isOF);
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set_register(r1, r2_val + r3_val);
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} else if (SGRK == op) {
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bool isOF = CheckOverflowForIntSub(r2_val, r3_val, int64_t);
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SetS390ConditionCode<int64_t>(r2_val - r3_val, 0);
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SetS390OverflowCode(isOF);
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set_register(r1, r2_val - r3_val);
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} else {
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// Assume bitwise operation here
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uint64_t bitwise_result = 0;
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if (NGRK == op) {
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bitwise_result = r2_val & r3_val;
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} else if (OGRK == op) {
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bitwise_result = r2_val | r3_val;
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} else if (XGRK == op) {
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bitwise_result = r2_val ^ r3_val;
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}
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SetS390BitWiseConditionCode<uint64_t>(bitwise_result);
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set_register(r1, bitwise_result);
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}
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break;
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}
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case ALGRK:
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case SLGRK: {
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// 64-bit Non-clobbering unsigned arithmetics
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int r1 = rrfInst->R1Value();
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int r2 = rrfInst->R2Value();
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int r3 = rrfInst->R3Value();
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uint64_t r2_val = get_register(r2);
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uint64_t r3_val = get_register(r3);
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if (ALGRK == op) {
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bool isOF = CheckOverflowForUIntAdd(r2_val, r3_val);
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SetS390ConditionCode<uint64_t>(r2_val + r3_val, 0);
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SetS390OverflowCode(isOF);
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set_register(r1, r2_val + r3_val);
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} else if (SLGRK == op) {
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bool isOF = CheckOverflowForUIntSub(r2_val, r3_val);
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SetS390ConditionCode<uint64_t>(r2_val - r3_val, 0);
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SetS390OverflowCode(isOF);
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set_register(r1, r2_val - r3_val);
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}
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}
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case AGHI:
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case MGHI: {
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RIInstruction* riinst = reinterpret_cast<RIInstruction*>(instr);
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int32_t r1 = riinst->R1Value();
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int64_t i = static_cast<int64_t>(riinst->I2Value());
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int64_t r1_val = get_register(r1);
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bool isOF = false;
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switch (op) {
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case AGHI:
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isOF = CheckOverflowForIntAdd(r1_val, i, int64_t);
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r1_val += i;
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break;
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case MGHI:
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isOF = CheckOverflowForMul(r1_val, i);
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r1_val *= i;
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break; // no overflow indication is given
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default:
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break;
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}
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set_register(r1, r1_val);
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SetS390ConditionCode<int32_t>(r1_val, 0);
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SetS390OverflowCode(isOF);
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break;
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}
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default:
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UNREACHABLE();
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}
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return true;
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}
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/**
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* Decodes and simulates four byte arithmetic instructions
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*/
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bool Simulator::DecodeFourByteArithmetic(Instruction* instr) {
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Opcode op = instr->S390OpcodeValue();
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// Pre-cast instruction to various types
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RRFInstruction* rrfInst = reinterpret_cast<RRFInstruction*>(instr);
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switch (op) {
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case AGR:
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case SGR:
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case OGR:
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case NGR:
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case XGR:
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case AGFR:
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case SGFR: {
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DecodeFourByteArithmetic64Bit(instr);
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break;
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}
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case ARK:
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case SRK:
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case NRK:
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@ -2599,56 +2700,12 @@ bool Simulator::DecodeFourByteArithmetic(Instruction* instr) {
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case NGRK:
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case OGRK:
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case XGRK: {
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// 64-bit Non-clobbering arithmetics / bitwise ops.
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int r1 = rrfInst->R1Value();
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int r2 = rrfInst->R2Value();
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int r3 = rrfInst->R3Value();
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int64_t r2_val = get_register(r2);
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int64_t r3_val = get_register(r3);
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if (AGRK == op) {
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bool isOF = CheckOverflowForIntAdd(r2_val, r3_val, int64_t);
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SetS390ConditionCode<int64_t>(r2_val + r3_val, 0);
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SetS390OverflowCode(isOF);
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set_register(r1, r2_val + r3_val);
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} else if (SGRK == op) {
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bool isOF = CheckOverflowForIntSub(r2_val, r3_val, int64_t);
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SetS390ConditionCode<int64_t>(r2_val - r3_val, 0);
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SetS390OverflowCode(isOF);
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set_register(r1, r2_val - r3_val);
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} else {
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// Assume bitwise operation here
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uint64_t bitwise_result = 0;
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if (NGRK == op) {
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bitwise_result = r2_val & r3_val;
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} else if (OGRK == op) {
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bitwise_result = r2_val | r3_val;
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} else if (XGRK == op) {
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bitwise_result = r2_val ^ r3_val;
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}
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SetS390BitWiseConditionCode<uint64_t>(bitwise_result);
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set_register(r1, bitwise_result);
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}
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DecodeFourByteArithmetic64Bit(instr);
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break;
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}
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case ALGRK:
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case SLGRK: {
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// 64-bit Non-clobbering unsigned arithmetics
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int r1 = rrfInst->R1Value();
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int r2 = rrfInst->R2Value();
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int r3 = rrfInst->R3Value();
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uint64_t r2_val = get_register(r2);
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uint64_t r3_val = get_register(r3);
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if (ALGRK == op) {
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bool isOF = CheckOverflowForUIntAdd(r2_val, r3_val);
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SetS390ConditionCode<uint64_t>(r2_val + r3_val, 0);
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SetS390OverflowCode(isOF);
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set_register(r1, r2_val + r3_val);
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} else if (SLGRK == op) {
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bool isOF = CheckOverflowForUIntSub(r2_val, r3_val);
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SetS390ConditionCode<uint64_t>(r2_val - r3_val, 0);
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SetS390OverflowCode(isOF);
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set_register(r1, r2_val - r3_val);
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}
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DecodeFourByteArithmetic64Bit(instr);
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break;
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}
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case AHI:
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@ -2677,26 +2734,7 @@ bool Simulator::DecodeFourByteArithmetic(Instruction* instr) {
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}
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case AGHI:
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case MGHI: {
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RIInstruction* riinst = reinterpret_cast<RIInstruction*>(instr);
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int32_t r1 = riinst->R1Value();
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int64_t i = static_cast<int64_t>(riinst->I2Value());
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int64_t r1_val = get_register(r1);
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bool isOF = false;
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switch (op) {
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case AGHI:
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isOF = CheckOverflowForIntAdd(r1_val, i, int64_t);
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r1_val += i;
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break;
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case MGHI:
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isOF = CheckOverflowForMul(r1_val, i);
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r1_val *= i;
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break; // no overflow indication is given
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default:
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break;
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}
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set_register(r1, r1_val);
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SetS390ConditionCode<int32_t>(r1_val, 0);
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SetS390OverflowCode(isOF);
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DecodeFourByteArithmetic64Bit(instr);
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break;
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}
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case MLR: {
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@ -2980,6 +3018,27 @@ bool Simulator::DecodeFourByteArithmetic(Instruction* instr) {
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#endif
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break;
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}
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case ALCR: {
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RREInstruction* rrinst = reinterpret_cast<RREInstruction*>(instr);
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int r1 = rrinst->R1Value();
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int r2 = rrinst->R2Value();
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uint32_t r1_val = get_low_register<uint32_t>(r1);
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uint32_t r2_val = get_low_register<uint32_t>(r2);
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uint32_t alu_out = 0;
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bool isOF = false;
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alu_out = r1_val + r2_val;
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bool isOF_original = CheckOverflowForUIntAdd(r1_val, r2_val);
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if (TestConditionCode((Condition)2) || TestConditionCode((Condition)3)) {
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alu_out = alu_out + 1;
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isOF = isOF_original || CheckOverflowForUIntAdd(alu_out, 1);
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} else {
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isOF = isOF_original;
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}
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set_low_register(r1, alu_out);
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SetS390ConditionCodeCarry<uint32_t>(alu_out, isOF);
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break;
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}
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default: { return DecodeFourByteFloatingPoint(instr); }
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}
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return true;
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@ -309,6 +309,7 @@ class Simulator {
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bool DecodeTwoByte(Instruction* instr);
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bool DecodeFourByte(Instruction* instr);
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bool DecodeFourByteArithmetic(Instruction* instr);
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bool DecodeFourByteArithmetic64Bit(Instruction* instr);
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bool DecodeFourByteFloatingPoint(Instruction* instr);
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void DecodeFourByteFloatingPointIntConversion(Instruction* instr);
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void DecodeFourByteFloatingPointRound(Instruction* instr);
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@ -395,6 +396,23 @@ class Simulator {
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if (condition_reg_ == 0) condition_reg_ = unordered;
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}
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// Used by arithmetic operations that use carry.
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template <typename T>
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void SetS390ConditionCodeCarry(T result, bool overflow) {
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condition_reg_ = 0;
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bool zero_result = (result == static_cast<T>(0));
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if (zero_result && !overflow) {
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condition_reg_ |= 8;
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} else if (!zero_result && !overflow) {
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condition_reg_ |= 4;
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} else if (zero_result && overflow) {
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condition_reg_ |= 2;
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} else if (!zero_result && overflow) {
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condition_reg_ |= 1;
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}
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if (condition_reg_ == 0) UNREACHABLE();
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}
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bool isNaN(double value) { return (value != value); }
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// Set the condition code for bitwise operations
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