From 8960f5d856cc526d5f66bd224cb1f7a5da1fdcbb Mon Sep 17 00:00:00 2001
From: "balazs.kilvady@imgtec.com" <balazs.kilvady@imgtec.com>
Date: Mon, 3 Nov 2014 16:40:54 +0000
Subject: [PATCH] MIPS: [turbofan] Also optimize unsigned division by constant.

Port r25061 (7fe697f)

TEST=cctest,mjsunit,unittests
BUG=
R=paul.lind@imgtec.com

Review URL: https://codereview.chromium.org/701543002

Cr-Commit-Position: refs/heads/master@{#25081}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25081 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
---
 src/compiler/mips/code-generator-mips.cc      |  3 +++
 src/compiler/mips/instruction-codes-mips.h    |  1 +
 .../mips/instruction-selector-mips.cc         |  7 ++++++
 src/mips/macro-assembler-mips.cc              | 22 +++++++++++++++++++
 src/mips/macro-assembler-mips.h               |  1 +
 5 files changed, 34 insertions(+)

diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index 9a8b98a635..2a07940473 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -188,6 +188,9 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kMipsMulHigh:
       __ Mulh(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       break;
+    case kMipsMulHighU:
+      __ Mulhu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+      break;
     case kMipsDiv:
       __ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       break;
diff --git a/src/compiler/mips/instruction-codes-mips.h b/src/compiler/mips/instruction-codes-mips.h
index 4c18ae1e5a..1e8be7ff67 100644
--- a/src/compiler/mips/instruction-codes-mips.h
+++ b/src/compiler/mips/instruction-codes-mips.h
@@ -18,6 +18,7 @@ namespace compiler {
   V(MipsSubOvf)                    \
   V(MipsMul)                       \
   V(MipsMulHigh)                   \
+  V(MipsMulHighU)                  \
   V(MipsDiv)                       \
   V(MipsDivU)                      \
   V(MipsMod)                       \
diff --git a/src/compiler/mips/instruction-selector-mips.cc b/src/compiler/mips/instruction-selector-mips.cc
index 637d98b784..f5a79ec30a 100644
--- a/src/compiler/mips/instruction-selector-mips.cc
+++ b/src/compiler/mips/instruction-selector-mips.cc
@@ -307,6 +307,13 @@ void InstructionSelector::VisitInt32MulHigh(Node* node) {
 }
 
 
+void InstructionSelector::VisitUint32MulHigh(Node* node) {
+  MipsOperandGenerator g(this);
+  Emit(kMipsMulHighU, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
+       g.UseRegister(node->InputAt(1)));
+}
+
+
 void InstructionSelector::VisitInt32Div(Node* node) {
   MipsOperandGenerator g(this);
   Int32BinopMatcher m(node);
diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc
index 03419cad03..a5af1b8d65 100644
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -740,6 +740,28 @@ void MacroAssembler::Mult(Register rs, const Operand& rt) {
 }
 
 
+void MacroAssembler::Mulhu(Register rd, Register rs, const Operand& rt) {
+  if (rt.is_reg()) {
+    if (!IsMipsArchVariant(kMips32r6)) {
+      multu(rs, rt.rm());
+      mfhi(rd);
+    } else {
+      muhu(rd, rs, rt.rm());
+    }
+  } else {
+    // li handles the relocation.
+    DCHECK(!rs.is(at));
+    li(at, rt);
+    if (!IsMipsArchVariant(kMips32r6)) {
+      multu(rs, at);
+      mfhi(rd);
+    } else {
+      muhu(rd, rs, at);
+    }
+  }
+}
+
+
 void MacroAssembler::Multu(Register rs, const Operand& rt) {
   if (rt.is_reg()) {
     multu(rs, rt.rm());
diff --git a/src/mips/macro-assembler-mips.h b/src/mips/macro-assembler-mips.h
index 9ee594ef95..d500eaa8bf 100644
--- a/src/mips/macro-assembler-mips.h
+++ b/src/mips/macro-assembler-mips.h
@@ -593,6 +593,7 @@ class MacroAssembler: public Assembler {
   DEFINE_INSTRUCTION(Modu);
   DEFINE_INSTRUCTION(Mulh);
   DEFINE_INSTRUCTION2(Mult);
+  DEFINE_INSTRUCTION(Mulhu);
   DEFINE_INSTRUCTION2(Multu);
   DEFINE_INSTRUCTION2(Div);
   DEFINE_INSTRUCTION2(Divu);