AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

PPC: [wasm-simd]Prototype load lane and store lane

Browse Source 
Prototype v128.{load,store}{8,16,32,64}_lane on arm.

Code for instruction selector is put in comments, will be moved
into instruction-scheduler-ppc.cc once we mark it as implemented
under instruction-scheduler.cc.

Bug: v8:10975
Change-Id: I43be8f32d0324ffb34220889365340e319fbb9d0
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2581622
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71683}
This commit is contained in:
Milad Fa 2020-12-09 13:20:04 -05:00 committed by Commit Bot
parent 53fb294334
commit 8a63801dd9
6 changed files with 141 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/codegen/ppc/assembler-ppc.cc
View File

@ -1825,6 +1825,30 @@ void Assembler::lxsiwzx(const Simd128Register rt, const MemOperand& src) {
src.rb().code() * B11 | TX);
}
void Assembler::stxsdx(const Simd128Register rs, const MemOperand& src) {
int SX = 1;
emit(STXSDX | rs.code() * B21 | src.ra().code() * B16 |
src.rb().code() * B11 | SX);
}
void Assembler::stxsibx(const Simd128Register rs, const MemOperand& src) {
int SX = 1;
emit(STXSIBX | rs.code() * B21 | src.ra().code() * B16 |
src.rb().code() * B11 | SX);
}
void Assembler::stxsihx(const Simd128Register rs, const MemOperand& src) {
int SX = 1;
emit(STXSIHX | rs.code() * B21 | src.ra().code() * B16 |
src.rb().code() * B11 | SX);
}
void Assembler::stxsiwx(const Simd128Register rs, const MemOperand& src) {
int SX = 1;
emit(STXSIWX | rs.code() * B21 | src.ra().code() * B16 |
src.rb().code() * B11 | SX);
}
void Assembler::stxvd(const Simd128Register rt, const MemOperand& dst) {
int SX = 1;
emit(STXVD | rt.code() * B21 | dst.ra().code() * B16 | dst.rb().code() * B11 |

4
src/codegen/ppc/assembler-ppc.h
View File

@ -1026,6 +1026,10 @@ class Assembler : public AssemblerBase {
void lxsibzx(const Simd128Register rt, const MemOperand& src);
void lxsihzx(const Simd128Register rt, const MemOperand& src);
void lxsiwzx(const Simd128Register rt, const MemOperand& src);
void stxsdx(const Simd128Register rs, const MemOperand& src);
void stxsibx(const Simd128Register rs, const MemOperand& src);
void stxsihx(const Simd128Register rs, const MemOperand& src);
void stxsiwx(const Simd128Register rs, const MemOperand& src);
void stxvd(const Simd128Register rt, const MemOperand& src);
void xxspltib(const Simd128Register rt, const Operand& imm);

4
src/codegen/ppc/constants-ppc.h
View File

@ -1999,6 +1999,10 @@ using Instr = uint32_t;
V(stxsdx, STXSDX, 0x7C000598) \
/* Store VSX Scalar as Integer Word Indexed */ \
V(stxsiwx, STXSIWX, 0x7C000118) \
/* Store VSX Scalar as Integer Halfword Indexed */ \
V(stxsihx, STXSIHX, 0x7C00075A) \
/* Store VSX Scalar as Integer Byte Indexed */ \
V(stxsibx, STXSIBX, 0x7C00071A) \
/* Store VSR Scalar Word Indexed */ \
V(stxsspx, STXSSPX, 0x7C000518) \
/* Store VSR Vector Doubleword*2 Indexed */ \

93
src/compiler/backend/ppc/code-generator-ppc.cc
View File

@ -3580,6 +3580,99 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
#undef ASSEMBLE_LOAD_TRANSFORM
case kPPC_S128Load8Lane: {
Simd128Register dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
AddressingMode mode = kMode_None;
size_t index = 1;
MemOperand operand = i.MemoryOperand(&mode, &index);
DCHECK_EQ(mode, kMode_MRR);
__ lxsibzx(kScratchDoubleReg, operand);
__ vinsertb(dst, kScratchDoubleReg, Operand(15 - i.InputUint8(3)));
break;
}
case kPPC_S128Load16Lane: {
Simd128Register dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
constexpr int lane_width_in_bytes = 2;
AddressingMode mode = kMode_None;
size_t index = 1;
MemOperand operand = i.MemoryOperand(&mode, &index);
DCHECK_EQ(mode, kMode_MRR);
__ lxsihzx(kScratchDoubleReg, operand);
__ vinserth(dst, kScratchDoubleReg,
Operand((7 - i.InputUint8(3)) * lane_width_in_bytes));
break;
}
case kPPC_S128Load32Lane: {
Simd128Register dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
constexpr int lane_width_in_bytes = 4;
AddressingMode mode = kMode_None;
size_t index = 1;
MemOperand operand = i.MemoryOperand(&mode, &index);
DCHECK_EQ(mode, kMode_MRR);
__ lxsiwzx(kScratchDoubleReg, operand);
__ vinsertw(dst, kScratchDoubleReg,
Operand((3 - i.InputUint8(3)) * lane_width_in_bytes));
break;
}
case kPPC_S128Load64Lane: {
Simd128Register dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
constexpr int lane_width_in_bytes = 8;
AddressingMode mode = kMode_None;
size_t index = 1;
MemOperand operand = i.MemoryOperand(&mode, &index);
DCHECK_EQ(mode, kMode_MRR);
__ lxsdx(kScratchDoubleReg, operand);
__ vinsertd(dst, kScratchDoubleReg,
Operand((1 - i.InputUint8(3)) * lane_width_in_bytes));
break;
}
case kPPC_S128Store8Lane: {
AddressingMode mode = kMode_None;
size_t index = 1;
MemOperand operand = i.MemoryOperand(&mode, &index);
DCHECK_EQ(mode, kMode_MRR);
__ vextractub(kScratchDoubleReg, i.InputSimd128Register(0),
Operand(15 - i.InputInt8(3)));
__ stxsibx(kScratchDoubleReg, operand);
break;
}
case kPPC_S128Store16Lane: {
AddressingMode mode = kMode_None;
constexpr int lane_width_in_bytes = 2;
size_t index = 1;
MemOperand operand = i.MemoryOperand(&mode, &index);
DCHECK_EQ(mode, kMode_MRR);
__ vextractuh(kScratchDoubleReg, i.InputSimd128Register(0),
Operand((7 - i.InputUint8(3)) * lane_width_in_bytes));
__ stxsihx(kScratchDoubleReg, operand);
break;
}
case kPPC_S128Store32Lane: {
AddressingMode mode = kMode_None;
constexpr int lane_width_in_bytes = 4;
size_t index = 1;
MemOperand operand = i.MemoryOperand(&mode, &index);
DCHECK_EQ(mode, kMode_MRR);
__ vextractuw(kScratchDoubleReg, i.InputSimd128Register(0),
Operand((3 - i.InputUint8(3)) * lane_width_in_bytes));
__ stxsiwx(kScratchDoubleReg, operand);
break;
}
case kPPC_S128Store64Lane: {
AddressingMode mode = kMode_None;
constexpr int lane_width_in_bytes = 8;
size_t index = 1;
MemOperand operand = i.MemoryOperand(&mode, &index);
DCHECK_EQ(mode, kMode_MRR);
__ vextractd(kScratchDoubleReg, i.InputSimd128Register(0),
Operand((1 - i.InputUint8(3)) * lane_width_in_bytes));
__ stxsdx(kScratchDoubleReg, operand);
break;
}
case kPPC_StoreCompressTagged: {
ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
break;

8
src/compiler/backend/ppc/instruction-codes-ppc.h
View File

@ -392,6 +392,14 @@ namespace compiler {
V(PPC_S128Load32x2U) \
V(PPC_S128Load32Zero) \
V(PPC_S128Load64Zero) \
V(PPC_S128Load8Lane) \
V(PPC_S128Load16Lane) \
V(PPC_S128Load32Lane) \
V(PPC_S128Load64Lane) \
V(PPC_S128Store8Lane) \
V(PPC_S128Store16Lane) \
V(PPC_S128Store32Lane) \
V(PPC_S128Store64Lane) \
V(PPC_StoreCompressTagged) \
V(PPC_LoadDecompressTaggedSigned) \
V(PPC_LoadDecompressTaggedPointer) \

8
src/compiler/backend/ppc/instruction-scheduler-ppc.cc
View File

@ -335,6 +335,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_S128Load32x2U:
case kPPC_S128Load32Zero:
case kPPC_S128Load64Zero:
case kPPC_S128Load8Lane:
case kPPC_S128Load16Lane:
case kPPC_S128Load32Lane:
case kPPC_S128Load64Lane:
return kIsLoadOperation;
case kPPC_StoreWord8:
@ -349,6 +353,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_PushFrame:
case kPPC_StoreToStackSlot:
case kPPC_Sync:
case kPPC_S128Store8Lane:
case kPPC_S128Store16Lane:
case kPPC_S128Store32Lane:
case kPPC_S128Store64Lane:
return kHasSideEffect;
case kPPC_AtomicStoreUint8: