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Clean up unused stuff in atomicops_internals_{tsan,x86_gcc}.h

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This ports crrev.com/278081 and crrev.com/271506 to V8.

R=glider@chromium.org, svenpanne@chromium.org

Review URL: https://codereview.chromium.org/342323002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21901 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
jkummerow@chromium.org 2014-06-20 12:58:48 +00:00
parent 0f8251e1b8
commit 8a9406017c
3 changed files with 1 additions and 47 deletions
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16
src/base/atomicops_internals_tsan.h
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@ -15,20 +15,6 @@ namespace base {
#ifndef TSAN_INTERFACE_ATOMIC_H
#define TSAN_INTERFACE_ATOMIC_H
// This struct is not part of the public API of this module; clients may not
// use it. (However, it's exported via BASE_EXPORT because clients implicitly
// do use it at link time by inlining these functions.)
// Features of this x86. Values may not be correct before main() is run,
// but are set conservatively.
struct AtomicOps_x86CPUFeatureStruct {
bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
// after acquire compare-and-swap.
bool has_sse2; // Processor has SSE2.
};
extern struct AtomicOps_x86CPUFeatureStruct
AtomicOps_Internalx86CPUFeatures;
#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
extern "C" {
typedef char __tsan_atomic8;
@ -374,6 +360,4 @@ inline void MemoryBarrier() {
} // namespace base
} // namespace v8
#undef ATOMICOPS_COMPILER_BARRIER
#endif // V8_BASE_ATOMICOPS_INTERNALS_TSAN_H_

4
src/base/atomicops_internals_x86_gcc.cc
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@ -42,7 +42,6 @@ namespace base {
// default values should hopefully be pretty safe.
struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
false, // bug can't exist before process spawns multiple threads
false, // no SSE2
};
} } // namespace v8::base
@ -88,9 +87,6 @@ void AtomicOps_Internalx86CPUFeaturesInit() {
} else {
AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
}
// edx bit 26 is SSE2 which we use to tell use whether we can use mfence
AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
}
class AtomicOpsx86Initializer {

28
src/base/atomicops_internals_x86_gcc.h
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@ -17,7 +17,6 @@ namespace base {
struct AtomicOps_x86CPUFeatureStruct {
bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
// after acquire compare-and-swap.
bool has_sse2; // Processor has SSE2.
};
extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
@ -92,10 +91,7 @@ inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
*ptr = value;
}
#if defined(__x86_64__)
// 64-bit implementations of memory barrier can be simpler, because it
// "mfence" is guaranteed to exist.
// We require SSE2, so mfence is guaranteed to exist.
inline void MemoryBarrier() {
__asm__ __volatile__("mfence" : : : "memory");
}
@ -105,28 +101,6 @@ inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
MemoryBarrier();
}
#else
inline void MemoryBarrier() {
if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
__asm__ __volatile__("mfence" : : : "memory");
} else { // mfence is faster but not present on PIII
Atomic32 x = 0;
NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
}
}
inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
*ptr = value;
__asm__ __volatile__("mfence" : : : "memory");
} else {
NoBarrier_AtomicExchange(ptr, value);
// acts as a barrier on PIII
}
}
#endif
inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
ATOMICOPS_COMPILER_BARRIER();
*ptr = value; // An x86 store acts as a release barrier.