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[riscv64] Use macros to control the compilation of RVV

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Change-Id: Iac021f8666058042f5c26cf07d0f3810a1d451fc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3528374
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#79617}
This commit is contained in:
Lu Yahan 2022-03-18 11:19:09 +08:00 committed by V8 LUCI CQ
parent ee29e41953
commit 8bfffd6a61
4 changed files with 39 additions and 2 deletions
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3
BUILD.gn
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@ -1179,6 +1179,9 @@ config("toolchain") {
#FIXME: Temporarily use MIPS macro for the building.
defines += [ "CAN_USE_FPU_INSTRUCTIONS" ]
if (target_is_simulator) {
defines += [ "CAN_USE_RVV_INSTRUCTIONS" ]
}
}
if (v8_current_cpu == "x86") {

2
src/codegen/riscv64/assembler-riscv64.cc
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@ -57,7 +57,7 @@ static unsigned CpuFeaturesImpliedByCompiler() {
answer |= 1u << FPU;
#endif // def CAN_USE_FPU_INSTRUCTIONS
#if (defined CAN_USE_RVV_INSTRUCTIONS) || (defined USE_SIMULATOR)
#if (defined CAN_USE_RVV_INSTRUCTIONS)
answer |= 1u << RISCV_SIMD;
#endif // def CAN_USE_RVV_INSTRUCTIONS || USE_SIMULATOR
return answer;

28
src/execution/riscv64/simulator-riscv64.cc
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@ -155,6 +155,7 @@ static inline bool is_overlapped_widen(const int astart, int asize,
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
#ifdef CAN_USE_RVV_INSTRUCTIONS
template <uint64_t N>
struct type_usew_t;
template <>
@ -1431,6 +1432,7 @@ inline Dst unsigned_saturation(Src v, uint n) {
} \
RVV_VI_LOOP_END \
rvv_trace_vd();
#endif
namespace v8 {
namespace internal {
@ -1488,7 +1490,9 @@ class RiscvDebugger {
int64_t GetFPURegisterValue(int regnum);
float GetFPURegisterValueFloat(int regnum);
double GetFPURegisterValueDouble(int regnum);
#ifdef CAN_USE_RVV_INSTRUCTIONS
__int128_t GetVRegisterValue(int regnum);
#endif
bool GetValue(const char* desc, int64_t* value);
};
@ -1529,6 +1533,7 @@ double RiscvDebugger::GetFPURegisterValueDouble(int regnum) {
}
}
#ifdef CAN_USE_RVV_INSTRUCTIONS
__int128_t RiscvDebugger::GetVRegisterValue(int regnum) {
if (regnum == kNumVRegisters) {
return sim_->get_pc();
@ -1536,6 +1541,7 @@ __int128_t RiscvDebugger::GetVRegisterValue(int regnum) {
return sim_->get_vregister(regnum);
}
}
#endif
bool RiscvDebugger::GetValue(const char* desc, int64_t* value) {
int regnum = Registers::Number(desc);
@ -1695,8 +1701,9 @@ void RiscvDebugger::Debug() {
} else {
int regnum = Registers::Number(arg1);
int fpuregnum = FPURegisters::Number(arg1);
#ifdef CAN_USE_RVV_INSTRUCTIONS
int vregnum = VRegisters::Number(arg1);
#endif
if (regnum != kInvalidRegister) {
value = GetRegisterValue(regnum);
PrintF("%s: 0x%08" PRIx64 " %" PRId64 " \n", arg1, value,
@ -1706,11 +1713,13 @@ void RiscvDebugger::Debug() {
dvalue = GetFPURegisterValueDouble(fpuregnum);
PrintF("%3s: 0x%016" PRIx64 " %16.4e\n",
FPURegisters::Name(fpuregnum), value, dvalue);
#ifdef CAN_USE_RVV_INSTRUCTIONS
} else if (vregnum != kInvalidVRegister) {
__int128_t v = GetVRegisterValue(vregnum);
PrintF("\t%s:0x%016" PRIx64 "%016" PRIx64 "\n",
VRegisters::Name(vregnum), (uint64_t)(v >> 64),
(uint64_t)v);
#endif
} else {
PrintF("%s unrecognized\n", arg1);
}
@ -2346,10 +2355,12 @@ double Simulator::get_fpu_register_double(int fpureg) const {
return *bit_cast<double*>(&FPUregisters_[fpureg]);
}
#ifdef CAN_USE_RVV_INSTRUCTIONS
__int128_t Simulator::get_vregister(int vreg) const {
DCHECK((vreg >= 0) && (vreg < kNumVRegisters));
return Vregister_[vreg];
}
#endif
// Runtime FP routines take up to two double arguments and zero
// or one integer arguments. All are constructed here,
@ -4255,6 +4266,7 @@ void Simulator::DecodeRVR4Type() {
}
}
#ifdef CAN_USE_RVV_INSTRUCTIONS
bool Simulator::DecodeRvvVL() {
uint32_t instr_temp =
instr_.InstructionBits() & (kRvvMopMask | kRvvNfMask | kBaseOpcodeMask);
@ -4381,6 +4393,7 @@ bool Simulator::DecodeRvvVS() {
return false;
}
}
#endif
Builtin Simulator::LookUp(Address pc) {
for (Builtin builtin = Builtins::kFirst; builtin <= Builtins::kLast;
@ -4618,9 +4631,13 @@ void Simulator::DecodeRVIType() {
break;
}
default: {
#ifdef CAN_USE_RVV_INSTRUCTIONS
if (!DecodeRvvVL()) {
UNSUPPORTED();
}
#else
UNSUPPORTED();
#endif
break;
}
}
@ -4655,9 +4672,13 @@ void Simulator::DecodeRVSType() {
break;
}
default:
#ifdef CAN_USE_RVV_INSTRUCTIONS
if (!DecodeRvvVS()) {
UNSUPPORTED();
}
#else
UNSUPPORTED();
#endif
break;
}
}
@ -5036,6 +5057,7 @@ T sat_subu(T x, T y, bool& sat) {
return res;
}
#ifdef CAN_USE_RVV_INSTRUCTIONS
void Simulator::DecodeRvvIVV() {
DCHECK_EQ(instr_.InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_IVV);
switch (instr_.InstructionBits() & kVTypeMask) {
@ -6839,6 +6861,8 @@ void Simulator::DecodeVType() {
FATAL("Error: Unsupport on FILE:%s:%d.", __FILE__, __LINE__);
}
}
#endif
// Executes the current instruction.
void Simulator::InstructionDecode(Instruction* instr) {
if (v8::internal::FLAG_check_icache) {
@ -6909,9 +6933,11 @@ void Simulator::InstructionDecode(Instruction* instr) {
case Instruction::kCSType:
DecodeCSType();
break;
#ifdef CAN_USE_RVV_INSTRUCTIONS
case Instruction::kVType:
DecodeVType();
break;
#endif
default:
if (1) {
std::cout << "Unrecognized instruction [@pc=0x" << std::hex

8
src/execution/riscv64/simulator-riscv64.h
View File

@ -380,6 +380,7 @@ class Simulator : public SimulatorBase {
void set_fflags(uint32_t flags) { set_csr_bits(csr_fflags, flags); }
void clear_fflags(int32_t flags) { clear_csr_bits(csr_fflags, flags); }
#ifdef CAN_USE_RVV_INSTRUCTIONS
// RVV CSR
__int128_t get_vregister(int vreg) const;
inline uint64_t rvv_vlen() const { return kRvvVLEN; }
@ -439,6 +440,7 @@ class Simulator : public SimulatorBase {
return ((rvv_vlen() << rvv_vlmul()) / rvv_sew());
}
}
#endif
inline uint32_t get_dynamic_rounding_mode();
inline bool test_fflags_bits(uint32_t mask);
@ -652,6 +654,7 @@ class Simulator : public SimulatorBase {
}
}
#ifdef CAN_USE_RVV_INSTRUCTIONS
inline void rvv_trace_vd() {
if (::v8::internal::FLAG_trace_sim) {
__int128_t value = Vregister_[rvv_vd_reg()];
@ -746,6 +749,7 @@ class Simulator : public SimulatorBase {
inline void set_rvv_vlenb(uint64_t value, bool trace = true) {
vlenb_ = value;
}
#endif
template <typename T, typename Func>
inline T CanonicalizeFPUOpFMA(Func fn, T dst, T src1, T src2) {
@ -862,6 +866,7 @@ class Simulator : public SimulatorBase {
void DecodeCSType();
void DecodeCJType();
void DecodeCBType();
#ifdef CAN_USE_RVV_INSTRUCTIONS
void DecodeVType();
void DecodeRvvIVV();
void DecodeRvvIVI();
@ -872,6 +877,7 @@ class Simulator : public SimulatorBase {
void DecodeRvvFVF();
bool DecodeRvvVL();
bool DecodeRvvVS();
#endif
// Used for breakpoints and traps.
void SoftwareInterrupt();
@ -938,10 +944,12 @@ class Simulator : public SimulatorBase {
// Floating-point control and status register.
uint32_t FCSR_;
#ifdef CAN_USE_RVV_INSTRUCTIONS
// RVV registers
__int128_t Vregister_[kNumVRegisters];
static_assert(sizeof(__int128_t) == kRvvVLEN / 8, "unmatch vlen");
uint64_t vstart_, vxsat_, vxrm_, vcsr_, vtype_, vl_, vlenb_;
#endif
// Simulator support.
// Allocate 1MB for stack.
size_t stack_size_;