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Reuse EncodeNeonUnaryOp for vrintp assembler

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Refer to "Advanced SIMD two registers misc", ARM DDI 0487F.b F4-4228.

Also moved the method down to the section with all the NEON
instructions, matching where the declaration in assembler-arm.h is.

Bug: v8:10553
Change-Id: I450edbfc3eafead4aad419299c93e43bd9d83133
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2252764
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#68442}
This commit is contained in:
Ng Zhi An 2020-06-18 13:26:57 -07:00 committed by Commit Bot
parent 5b76903452
commit 8d6a0b2b32
1 changed files with 12 additions and 18 deletions
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30
src/codegen/arm/assembler-arm.cc
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@ -3596,23 +3596,6 @@ void Assembler::vrintp(const DwVfpRegister dst, const DwVfpRegister src) {
vd * B12 | 0x5 * B9 | B8 | B6 | m * B5 | vm);
}
void Assembler::vrintp(NeonDataType dt, const QwNeonRegister dst,
const QwNeonRegister src) {
// cond=kSpecialCondition(31-28) | 00111(27-23)| D(22) | 11(21-20) |
// size(19-18) | 10(17-16) | Vd(15-12) | 01(11-10) | 7(9-7) | 1(6) | M(5) |
// 0(4) | Vm(3-0)
DCHECK(IsEnabled(ARMv8));
int vd, d;
dst.split_code(&vd, &d);
int vm, m;
src.split_code(&vm, &m);
int size = NeonSz(dt);
// Only F32 is implemented for now.
DCHECK_EQ(0x2, dt);
emit(kSpecialCondition | 0x7 * B23 | d * B22 | 0x3 * B20 | size * B18 |
0x2 * B16 | vd * B12 | 0x1 * B10 | 0x7 * B7 | B6 | m * B5 | vm);
}
void Assembler::vrintm(const SwVfpRegister dst, const SwVfpRegister src) {
// cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
// 10(19-18) | RM=11(17-16) | Vd(15-12) | 101(11-9) | sz=0(8) | 01(7-6) |
@ -3909,7 +3892,7 @@ void Assembler::vcvt_u32_f32(QwNeonRegister dst, QwNeonRegister src) {
emit(EncodeNeonVCVT(U32, dst, F32, src));
}
enum UnaryOp { VMVN, VSWP, VABS, VABSF, VNEG, VNEGF };
enum UnaryOp { VMVN, VSWP, VABS, VABSF, VNEG, VNEGF, VRINTP };
static Instr EncodeNeonUnaryOp(UnaryOp op, NeonRegType reg_type, NeonSize size,
int dst_code, int src_code) {
@ -3937,6 +3920,9 @@ static Instr EncodeNeonUnaryOp(UnaryOp op, NeonRegType reg_type, NeonSize size,
DCHECK_EQ(Neon32, size);
op_encoding = B16 | B10 | 0x7 * B7;
break;
case VRINTP:
op_encoding = B17 | 0xF * B7;
break;
default:
UNREACHABLE();
}
@ -4592,6 +4578,14 @@ void Assembler::vpmax(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1,
emit(EncodeNeonPairwiseOp(VPMAX, dt, dst, src1, src2));
}
void Assembler::vrintp(NeonDataType dt, const QwNeonRegister dst,
const QwNeonRegister src) {
// SIMD vector round floating-point to integer towards +Infinity.
// See ARM DDI 0487F.b, F6-5501
DCHECK(IsEnabled(ARMv8));
emit(EncodeNeonUnaryOp(VRINTP, NEON_Q, NeonSize(dt), dst.code(), src.code()));
}
void Assembler::vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
QwNeonRegister src2) {
DCHECK(IsEnabled(NEON));