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Add ARMv8 detection in CpuFeatures.

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R=rodolph.perfetta@arm.com, ulan@chromium.org

Review URL: https://codereview.chromium.org/678313002

Cr-Commit-Position: refs/heads/master@{#24949}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24949 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
sigurds@chromium.org 2014-10-28 15:22:22 +00:00
parent b4799b8d1f
commit 8ef8f58bae
3 changed files with 33 additions and 22 deletions
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3
src/arm/assembler-arm.cc
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@ -109,6 +109,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
if (cpu.architecture() >= 7) {
if (FLAG_enable_armv7) supported_ |= 1u << ARMv7;
if (FLAG_enable_armv8 && cpu.architecture() >= 8) {
supported_ |= 1u << ARMv8;
}
if (FLAG_enable_unaligned_accesses) supported_ |= 1u << UNALIGNED_ACCESSES;
// Use movw/movt for QUALCOMM ARMv7 cores.
if (FLAG_enable_movw_movt && cpu.implementer() == base::CPU::QUALCOMM) {

7
src/flag-definitions.h
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@ -114,6 +114,11 @@ struct MaybeBoolFlag {
#else
#define ENABLE_ARMV7_DEFAULT false
#endif
#if (defined CAN_USE_ARMV8_INSTRUCTIONS) || !(defined ARM_TEST_NO_FEATURE_PROBE)
#define ENABLE_ARMV8_DEFAULT true
#else
#define ENABLE_ARMV8_DEFAULT false
#endif
#if (defined CAN_USE_VFP32DREGS) || !(defined ARM_TEST_NO_FEATURE_PROBE)
#define ENABLE_32DREGS_DEFAULT true
#else
@ -402,6 +407,8 @@ DEFINE_BOOL(enable_vfp3, ENABLE_VFP3_DEFAULT,
"enable use of VFP3 instructions if available")
DEFINE_BOOL(enable_armv7, ENABLE_ARMV7_DEFAULT,
"enable use of ARMv7 instructions if available (ARM only)")
DEFINE_BOOL(enable_armv8, ENABLE_ARMV8_DEFAULT,
"enable use of ARMv8 instructions if available (ARM 32-bit only)")
DEFINE_BOOL(enable_neon, ENABLE_NEON_DEFAULT,
"enable use of NEON instructions if available (ARM only)")
DEFINE_BOOL(enable_sudiv, true,

45
src/globals.h
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@ -609,28 +609,29 @@ struct AccessorDescriptor {
// CPU feature flags.
enum CpuFeature {
// x86
SSE4_1,
SSE3,
SAHF,
// ARM
VFP3,
ARMv7,
SUDIV,
MLS,
UNALIGNED_ACCESSES,
MOVW_MOVT_IMMEDIATE_LOADS,
VFP32DREGS,
NEON,
// MIPS, MIPS64
FPU,
FP64FPU,
MIPSr1,
MIPSr2,
MIPSr6,
// ARM64
ALWAYS_ALIGN_CSP,
NUMBER_OF_CPU_FEATURES
// x86
SSE4_1,
SSE3,
SAHF,
// ARM
VFP3,
ARMv7,
ARMv8,
SUDIV,
MLS,
UNALIGNED_ACCESSES,
MOVW_MOVT_IMMEDIATE_LOADS,
VFP32DREGS,
NEON,
// MIPS, MIPS64
FPU,
FP64FPU,
MIPSr1,
MIPSr2,
MIPSr6,
// ARM64
ALWAYS_ALIGN_CSP,
NUMBER_OF_CPU_FEATURES
};