[ia32][x64] Detect AVX2

- Add the appropriate cpuid checks to detect AVX2 in base/cpu
- Add FLAG_enable_avx2

AVX2 depends on AVX support, + a cpuid check with eax=7. This is similar
to chromium/src/base/cpu.cc check for AVX2.

Bug: v8:11258
Change-Id: Ia547c22e51b03fec823f5e48ebb055139632c942
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2589050
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71821}
This commit is contained in:
Zhi An Ng 2020-12-14 02:23:07 +00:00 committed by Commit Bot
parent 46ce9b0554
commit 8f02ad408e
7 changed files with 32 additions and 8 deletions

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@ -383,6 +383,7 @@ bool CPU::StarboardDetectCPU() {
has_sse41_ = features.x86.has_sse41;
has_sahf_ = features.x86.has_sahf;
has_avx_ = features.x86.has_avx;
has_avx2_ = features.x86.has_avx2;
has_fma3_ = features.x86.has_fma3;
has_bmi1_ = features.x86.has_bmi1;
has_bmi2_ = features.x86.has_bmi2;
@ -427,6 +428,7 @@ CPU::CPU()
is_atom_(false),
has_osxsave_(false),
has_avx_(false),
has_avx2_(false),
has_fma3_(false),
has_bmi1_(false),
has_bmi2_(false),
@ -469,6 +471,12 @@ CPU::CPU()
// Interpret CPU feature information.
if (num_ids > 0) {
__cpuid(cpu_info, 1);
int cpu_info7[4] = {0};
if (num_ids >= 7) {
__cpuid(cpu_info7, 7);
}
stepping_ = cpu_info[0] & 0xF;
model_ = ((cpu_info[0] >> 4) & 0xF) + ((cpu_info[0] >> 12) & 0xF0);
family_ = (cpu_info[0] >> 8) & 0xF;
@ -487,6 +495,7 @@ CPU::CPU()
has_popcnt_ = (cpu_info[2] & 0x00800000) != 0;
has_osxsave_ = (cpu_info[2] & 0x08000000) != 0;
has_avx_ = (cpu_info[2] & 0x10000000) != 0;
has_avx2_ = (cpu_info7[1] & 0x00000020) != 0;
has_fma3_ = (cpu_info[2] & 0x00001000) != 0;
if (family_ == 0x6) {

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@ -93,6 +93,7 @@ class V8_BASE_EXPORT CPU final {
bool has_sse42() const { return has_sse42_; }
bool has_osxsave() const { return has_osxsave_; }
bool has_avx() const { return has_avx_; }
bool has_avx2() const { return has_avx2_; }
bool has_fma3() const { return has_fma3_; }
bool has_bmi1() const { return has_bmi1_; }
bool has_bmi2() const { return has_bmi2_; }
@ -143,6 +144,7 @@ class V8_BASE_EXPORT CPU final {
bool is_atom_;
bool has_osxsave_;
bool has_avx_;
bool has_avx2_;
bool has_fma3_;
bool has_bmi1_;
bool has_bmi2_;

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@ -20,6 +20,7 @@ enum CpuFeature {
SSE3,
SAHF,
AVX,
AVX2,
FMA3,
BMI1,
BMI2,

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@ -137,6 +137,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
OSHasAVXSupport()) {
supported_ |= 1u << AVX;
}
if (cpu.has_avx2() && FLAG_enable_avx2 && IsSupported(AVX)) {
supported_ |= 1u << AVX2;
}
if (cpu.has_fma3() && FLAG_enable_fma3 && cpu.has_osxsave() &&
OSHasAVXSupport()) {
supported_ |= 1u << FMA3;
@ -155,13 +158,15 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
void CpuFeatures::PrintTarget() {}
void CpuFeatures::PrintFeatures() {
printf(
"SSE3=%d SSSE3=%d SSE4_1=%d AVX=%d FMA3=%d BMI1=%d BMI2=%d LZCNT=%d "
"SSE3=%d SSSE3=%d SSE4_1=%d AVX=%d AVX2=%d FMA3=%d BMI1=%d BMI2=%d "
"LZCNT=%d "
"POPCNT=%d ATOM=%d\n",
CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSSE3),
CpuFeatures::IsSupported(SSE4_1), CpuFeatures::IsSupported(AVX),
CpuFeatures::IsSupported(FMA3), CpuFeatures::IsSupported(BMI1),
CpuFeatures::IsSupported(BMI2), CpuFeatures::IsSupported(LZCNT),
CpuFeatures::IsSupported(POPCNT), CpuFeatures::IsSupported(ATOM));
CpuFeatures::IsSupported(AVX2), CpuFeatures::IsSupported(FMA3),
CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2),
CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT),
CpuFeatures::IsSupported(ATOM));
}
// -----------------------------------------------------------------------------

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@ -92,6 +92,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
OSHasAVXSupport()) {
supported_ |= 1u << AVX;
}
if (cpu.has_avx2() && FLAG_enable_avx2 && IsSupported(AVX)) {
supported_ |= 1u << AVX2;
}
if (cpu.has_fma3() && FLAG_enable_fma3 && cpu.has_osxsave() &&
OSHasAVXSupport()) {
supported_ |= 1u << FMA3;
@ -110,16 +113,18 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
void CpuFeatures::PrintTarget() {}
void CpuFeatures::PrintFeatures() {
printf(
"SSE3=%d SSSE3=%d SSE4_1=%d SSE4_2=%d SAHF=%d AVX=%d FMA3=%d BMI1=%d "
"SSE3=%d SSSE3=%d SSE4_1=%d SSE4_2=%d SAHF=%d AVX=%d AVX2=%d FMA3=%d "
"BMI1=%d "
"BMI2=%d "
"LZCNT=%d "
"POPCNT=%d ATOM=%d\n",
CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSSE3),
CpuFeatures::IsSupported(SSE4_1), CpuFeatures::IsSupported(SSE4_2),
CpuFeatures::IsSupported(SAHF), CpuFeatures::IsSupported(AVX),
CpuFeatures::IsSupported(FMA3), CpuFeatures::IsSupported(BMI1),
CpuFeatures::IsSupported(BMI2), CpuFeatures::IsSupported(LZCNT),
CpuFeatures::IsSupported(POPCNT), CpuFeatures::IsSupported(ATOM));
CpuFeatures::IsSupported(AVX2), CpuFeatures::IsSupported(FMA3),
CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2),
CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT),
CpuFeatures::IsSupported(ATOM));
}
// -----------------------------------------------------------------------------

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@ -1188,6 +1188,7 @@ DEFINE_BOOL(enable_sse4_2, true,
DEFINE_BOOL(enable_sahf, true,
"enable use of SAHF instruction if available (X64 only)")
DEFINE_BOOL(enable_avx, true, "enable use of AVX instructions if available")
DEFINE_BOOL(enable_avx2, true, "enable use of AVX2 instructions if available")
DEFINE_BOOL(enable_fma3, true, "enable use of FMA3 instructions if available")
DEFINE_BOOL(enable_bmi1, true, "enable use of BMI1 instructions if available")
DEFINE_BOOL(enable_bmi2, true, "enable use of BMI2 instructions if available")

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@ -20,6 +20,7 @@ TEST(CPUTest, FeatureImplications) {
EXPECT_TRUE(!cpu.has_sse42() || cpu.has_sse41());
EXPECT_TRUE(!cpu.has_avx() || cpu.has_sse2());
EXPECT_TRUE(!cpu.has_fma3() || cpu.has_avx());
EXPECT_TRUE(!cpu.has_avx2() || cpu.has_avx());
// arm features
EXPECT_TRUE(!cpu.has_vfp3_d32() || cpu.has_vfp3());