MIPS:[turbofan] Improve unordered comparisons for boolean materialization.
TEST= BUG= R=paul.lind@imgtec.com Review URL: https://codereview.chromium.org/894883004 Cr-Commit-Position: refs/heads/master@{#26422}
This commit is contained in:
Dusan Milosavljevic
parent
d923864c79
commit
8f9a62d312
@ -262,6 +262,33 @@ Condition FlagsConditionToConditionOvf(FlagsCondition condition) {
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return kNoCondition;
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}
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FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
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FlagsCondition condition) {
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switch (condition) {
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case kEqual:
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predicate = true;
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return EQ;
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case kNotEqual:
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predicate = false;
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return EQ;
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case kUnsignedLessThan:
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predicate = true;
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return OLT;
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case kUnsignedLessThanOrEqual:
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predicate = true;
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return OLE;
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case kUnorderedEqual:
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case kUnorderedNotEqual:
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predicate = true;
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break;
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default:
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predicate = true;
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break;
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}
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UNREACHABLE();
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return kNoFPUCondition;
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}
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} // namespace
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@ -790,8 +817,6 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
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// in the false case, where we fall thru the branch, we reset the result
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// false.
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// TODO(plind): Add CHECK() to ensure that test/cmp and this branch were
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// not separated by other instructions.
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if (instr->arch_opcode() == kMipsTst) {
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cc = FlagsConditionToConditionTst(condition);
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__ And(at, i.InputRegister(0), i.InputOperand(1));
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@ -805,7 +830,6 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
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__ Branch(USE_DELAY_SLOT, &done, cc, kCompareReg, Operand(zero_reg));
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__ li(result, Operand(1)); // In delay slot.
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} else if (instr->arch_opcode() == kMipsCmp) {
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Register left = i.InputRegister(0);
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Operand right = i.InputOperand(1);
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@ -816,54 +840,33 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
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} else if (instr->arch_opcode() == kMipsCmpD) {
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FPURegister left = i.InputDoubleRegister(0);
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FPURegister right = i.InputDoubleRegister(1);
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// TODO(plind): Provide NaN-testing macro-asm function without need for
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// BranchF.
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FPURegister dummy1 = f0;
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FPURegister dummy2 = f2;
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switch (condition) {
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case kEqual:
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// TODO(plind): improve the NaN testing throughout this function.
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__ BranchF(NULL, &false_value, kNoCondition, dummy1, dummy2);
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cc = eq;
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break;
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case kNotEqual:
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__ BranchF(USE_DELAY_SLOT, NULL, &done, kNoCondition, dummy1, dummy2);
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__ li(result, Operand(1)); // In delay slot - returns 1 on NaN.
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cc = ne;
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break;
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case kUnsignedLessThan:
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__ BranchF(NULL, &false_value, kNoCondition, dummy1, dummy2);
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cc = lt;
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break;
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case kUnsignedGreaterThanOrEqual:
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__ BranchF(USE_DELAY_SLOT, NULL, &done, kNoCondition, dummy1, dummy2);
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__ li(result, Operand(1)); // In delay slot - returns 1 on NaN.
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cc = ge;
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break;
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case kUnsignedLessThanOrEqual:
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__ BranchF(NULL, &false_value, kNoCondition, dummy1, dummy2);
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cc = le;
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break;
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case kUnsignedGreaterThan:
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__ BranchF(USE_DELAY_SLOT, NULL, &done, kNoCondition, dummy1, dummy2);
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__ li(result, Operand(1)); // In delay slot - returns 1 on NaN.
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cc = gt;
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break;
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default:
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UNSUPPORTED_COND(kMipsCmp, condition);
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break;
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}
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__ BranchF(USE_DELAY_SLOT, &done, NULL, cc, left, right);
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__ li(result, Operand(1)); // In delay slot - branch taken returns 1.
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// Fall-thru (branch not taken) returns 0.
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bool predicate;
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FPUCondition cc = FlagsConditionToConditionCmpD(predicate, condition);
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if (!IsMipsArchVariant(kMips32r6)) {
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__ li(result, Operand(1));
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__ c(cc, D, left, right);
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if (predicate) {
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__ Movf(result, zero_reg);
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} else {
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__ Movt(result, zero_reg);
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}
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} else {
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__ cmp(cc, L, kDoubleCompareReg, left, right);
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__ mfc1(at, kDoubleCompareReg);
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__ srl(result, at, 31); // Cmp returns all 1s for true.
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if (!predicate) // Toggle result for not equal.
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__ xori(result, result, 1);
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}
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return;
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} else {
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PrintF("AssembleArchBranch Unimplemented arch_opcode is : %d\n",
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instr->arch_opcode());
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TRACE_UNIMPL();
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UNIMPLEMENTED();
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}
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// Fallthru case is the false materialization.
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// Fallthrough case is the false materialization.
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__ bind(&false_value);
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__ li(result, Operand(0));
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__ bind(&done);
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@ -262,6 +262,34 @@ Condition FlagsConditionToConditionOvf(FlagsCondition condition) {
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return kNoCondition;
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}
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FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
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FlagsCondition condition) {
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switch (condition) {
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case kEqual:
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predicate = true;
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return EQ;
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case kNotEqual:
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predicate = false;
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return EQ;
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case kUnsignedLessThan:
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predicate = true;
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return OLT;
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case kUnsignedLessThanOrEqual:
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predicate = true;
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return OLE;
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case kUnorderedEqual:
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case kUnorderedNotEqual:
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predicate = true;
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break;
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default:
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predicate = true;
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break;
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}
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UNREACHABLE();
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return kNoFPUCondition;
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}
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} // namespace
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@ -968,47 +996,25 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
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} else if (instr->arch_opcode() == kMips64CmpD) {
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FPURegister left = i.InputDoubleRegister(0);
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FPURegister right = i.InputDoubleRegister(1);
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// TODO(plind): Provide NaN-testing macro-asm function without need for
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// BranchF.
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FPURegister dummy1 = f0;
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FPURegister dummy2 = f2;
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switch (condition) {
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case kEqual:
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// TODO(plind): improve the NaN testing throughout this function.
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__ BranchF(NULL, &false_value, kNoCondition, dummy1, dummy2);
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cc = eq;
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break;
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case kNotEqual:
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__ BranchF(USE_DELAY_SLOT, NULL, &done, kNoCondition, dummy1, dummy2);
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__ li(result, Operand(1)); // In delay slot - returns 1 on NaN.
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cc = ne;
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break;
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case kUnsignedLessThan:
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__ BranchF(NULL, &false_value, kNoCondition, dummy1, dummy2);
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cc = lt;
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break;
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case kUnsignedGreaterThanOrEqual:
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__ BranchF(USE_DELAY_SLOT, NULL, &done, kNoCondition, dummy1, dummy2);
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__ li(result, Operand(1)); // In delay slot - returns 1 on NaN.
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cc = ge;
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break;
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case kUnsignedLessThanOrEqual:
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__ BranchF(NULL, &false_value, kNoCondition, dummy1, dummy2);
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cc = le;
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break;
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case kUnsignedGreaterThan:
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__ BranchF(USE_DELAY_SLOT, NULL, &done, kNoCondition, dummy1, dummy2);
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__ li(result, Operand(1)); // In delay slot - returns 1 on NaN.
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cc = gt;
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break;
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default:
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UNSUPPORTED_COND(kMips64Cmp, condition);
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break;
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}
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__ BranchF(USE_DELAY_SLOT, &done, NULL, cc, left, right);
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__ li(result, Operand(1)); // In delay slot - branch taken returns 1.
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// Fall-thru (branch not taken) returns 0.
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bool predicate;
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FPUCondition cc = FlagsConditionToConditionCmpD(predicate, condition);
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if (kArchVariant != kMips64r6) {
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__ li(result, Operand(1));
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__ c(cc, D, left, right);
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if (predicate) {
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__ Movf(result, zero_reg);
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} else {
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__ Movt(result, zero_reg);
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}
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} else {
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__ cmp(cc, L, kDoubleCompareReg, left, right);
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__ dmfc1(at, kDoubleCompareReg);
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__ dsrl32(result, at, 31); // Cmp returns all 1s for true.
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if (!predicate) // Toggle result for not equal.
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__ xori(result, result, 1);
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}
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return;
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} else {
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PrintF("AssembleArchBranch Unimplemented arch_opcode is : %d\n",
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instr->arch_opcode());
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@ -323,6 +323,8 @@ const FPURegister f31 = { 31 };
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#define kLithiumScratchReg2 s4
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#define kLithiumScratchDouble f30
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#define kDoubleRegZero f28
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// Used on mips64r6 for compare operations.
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#define kDoubleCompareReg f31
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// FPU (coprocessor 1) control registers.
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// Currently only FCSR (#31) is implemented.
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