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[mips] Fix floating point abs operation

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Float32/64 abs operation should only clear the sign bit, but abs.s
and abs.d instructions of mips64r2 would convert nan to canonical
nan.

Change-Id: Ibbd05cdb3a73acfe0e532030d1815d262c3ac433
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2439768
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70214}
This commit is contained in:
Zhao Jiazhong 2020-09-30 04:34:19 -04:00 committed by Commit Bot
parent 75b8c238dc
commit 90f9decefa
2 changed files with 28 additions and 4 deletions
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16
src/compiler/backend/mips/code-generator-mips.cc
View File

@ -1239,7 +1239,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kMipsAbsS: case kMipsAbsS:
__ abs_s(i.OutputSingleRegister(), i.InputSingleRegister(0)); if (IsMipsArchVariant(kMips32r6)) {
__ abs_s(i.OutputSingleRegister(), i.InputSingleRegister(0));
} else {
__ mfc1(kScratchReg, i.InputSingleRegister(0));
__ Ins(kScratchReg, zero_reg, 31, 1);
__ mtc1(kScratchReg, i.OutputSingleRegister());
}
break; break;
case kMipsSqrtS: { case kMipsSqrtS: {
__ sqrt_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); __ sqrt_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
@ -1331,7 +1337,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kMipsAbsD: case kMipsAbsD:
__ abs_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); if (IsMipsArchVariant(kMips32r6)) {
__ abs_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
} else {
__ mfhc1(kScratchReg, i.InputDoubleRegister(0));
__ Ins(kScratchReg, zero_reg, 31, 1);
__ mthc1(kScratchReg, i.OutputDoubleRegister());
}
break; break;
case kMipsNegS: case kMipsNegS:
__ Neg_s(i.OutputSingleRegister(), i.InputSingleRegister(0)); __ Neg_s(i.OutputSingleRegister(), i.InputSingleRegister(0));

16
src/compiler/backend/mips64/code-generator-mips64.cc
View File

@ -1318,7 +1318,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kMips64AbsS: case kMips64AbsS:
__ abs_s(i.OutputSingleRegister(), i.InputSingleRegister(0)); if (kArchVariant == kMips64r6) {
__ abs_s(i.OutputSingleRegister(), i.InputSingleRegister(0));
} else {
__ mfc1(kScratchReg, i.InputSingleRegister(0));
__ Dins(kScratchReg, zero_reg, 31, 1);
__ mtc1(kScratchReg, i.OutputSingleRegister());
}
break; break;
case kMips64NegS: case kMips64NegS:
__ Neg_s(i.OutputSingleRegister(), i.InputSingleRegister(0)); __ Neg_s(i.OutputSingleRegister(), i.InputSingleRegister(0));
@ -1378,7 +1384,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kMips64AbsD: case kMips64AbsD:
__ abs_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); if (kArchVariant == kMips64r6) {
__ abs_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
} else {
__ dmfc1(kScratchReg, i.InputDoubleRegister(0));
__ Dins(kScratchReg, zero_reg, 63, 1);
__ dmtc1(kScratchReg, i.OutputDoubleRegister());
}
break; break;
case kMips64NegD: case kMips64NegD:
__ Neg_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); __ Neg_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0));