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[riscv] Port [wasm][simd] Fix SpillAdjacentFpRegisters

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Port commit 8e069d6294

Bug:chromium:1356718

Change-Id: I0f9f19e45c8f3fc18b46ac0c1341cc61d5b1ae59
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3868714
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Jakob Kummerow <jkummerow@chromium.org>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Cr-Commit-Position: refs/heads/main@{#82926}
This commit is contained in:
Lu Yahan 2022-09-02 15:44:12 +08:00 committed by V8 LUCI CQ
parent eb107f6c5b
commit 931828a6a1
3 changed files with 13 additions and 1 deletions
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2
src/wasm/baseline/liftoff-assembler-defs.h
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@ -108,6 +108,8 @@ constexpr RegList kLiftoffAssemblerGpCacheRegs = {a0, a1, a2, a3, a4, a5,
// Any change of kLiftoffAssemblerGpCacheRegs also need to update
// kPushedFpRegs in frame-constants-riscv.h
// ft0 don't be putted int kLiftoffAssemblerFpCacheRegs because v0 is a special
// simd register and code of ft0 and v0 is same.
constexpr DoubleRegList kLiftoffAssemblerFpCacheRegs = {
ft1, ft2, ft3, ft4, ft5, ft6, ft7, fa0, fa1, fa2,
fa3, fa4, fa5, fa6, fa7, ft8, ft9, ft10, ft11};

3
src/wasm/baseline/liftoff-register.h
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@ -434,7 +434,8 @@ class LiftoffRegList {
constexpr LiftoffRegList SpreadSetBitsToAdjacentFpRegs() const {
storage_t odd_regs = regs_ & kOddFpSetMask;
storage_t even_regs = regs_ & kEvenFpSetMask;
return FromBits(regs_ | (odd_regs >> 1) | ((even_regs << 1) & kFpMask));
return FromBits(regs_ | ((odd_regs >> 1) & kFpMask) |
((even_regs << 1) & kFpMask));
}
constexpr bool operator==(const LiftoffRegList other) const {

9
test/unittests/wasm/liftoff-register-unittests.cc
View File

@ -50,6 +50,9 @@ TEST_F(WasmRegisterTest, SpreadSetBitsToAdjacentFpRegs) {
#if V8_TARGET_ARCH_S390X || V8_TARGET_ARCH_PPC64
LiftoffRegister::from_code(kGpReg, 4),
LiftoffRegister::from_code(kGpReg, 7),
#elif V8_TARGET_ARCH_RISCV32 || V8_TARGET_ARCH_RISCV64
LiftoffRegister::from_code(kGpReg, 10),
LiftoffRegister::from_code(kGpReg, 13),
#else
LiftoffRegister::from_code(kGpReg, 1),
LiftoffRegister::from_code(kGpReg, 2),
@ -58,9 +61,15 @@ TEST_F(WasmRegisterTest, SpreadSetBitsToAdjacentFpRegs) {
LiftoffRegister::from_code(kFpReg, 4));
// GP regs are left alone, FP regs are spread to adjacent pairs starting
// at an even index: 1 → (0, 1) and 4 → (4, 5).
#if V8_TARGET_ARCH_RISCV32 || V8_TARGET_ARCH_RISCV64
// RISCV don't have code 0 in kLiftoffAssemblerFpCacheRegs
LiftoffRegList expected =
input | LiftoffRegList(LiftoffRegister::from_code(kFpReg, 5));
#else
LiftoffRegList expected =
input | LiftoffRegList(LiftoffRegister::from_code(kFpReg, 0),
LiftoffRegister::from_code(kFpReg, 5));
#endif
LiftoffRegList actual = input.SpreadSetBitsToAdjacentFpRegs();
EXPECT_EQ(expected, actual);
}