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Ignore cache flush when running V8 arm64 backend under simulator

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When running under simulator, all arm64 JIT instructions are interpreted by
simulator via normal memory read, then no need to do icache/dcache flush.

Also when running under simulator, cache_type_register_ is set to 0 explicitly
in above CacheLineSizes class, which results in 0 value in both dstart and
istart, then causes flush on this incorrect range.

Bug: chromium:893460
Change-Id: Ief6cb09a0e89f7ede0761ad676ea6a882e9f4600
Reviewed-on: https://chromium-review.googlesource.com/c/1492514
Commit-Queue: Michael Lippautz <mlippautz@chromium.org>
Reviewed-by: Michael Lippautz <mlippautz@chromium.org>
Cr-Commit-Position: refs/heads/master@{#59987}
This commit is contained in:
Tom Tan 2019-02-28 12:46:50 -08:00 committed by Commit Bot
parent c0eb72e063
commit 9405fcfdd1
1 changed files with 4 additions and 2 deletions
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6
src/arm64/cpu-arm64.cc
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@ -15,7 +15,7 @@ namespace internal {
class CacheLineSizes {
public:
CacheLineSizes() {
#if defined(USE_SIMULATOR) || defined(V8_OS_WIN)
#if !defined(V8_HOST_ARCH_ARM64) || defined(V8_OS_WIN)
cache_type_register_ = 0;
#else
// Copy the content of the cache type register to a core register.
@ -38,9 +38,10 @@ class CacheLineSizes {
};
void CpuFeatures::FlushICache(void* address, size_t length) {
#if defined(V8_HOST_ARCH_ARM64)
#if defined(V8_OS_WIN)
::FlushInstructionCache(GetCurrentProcess(), address, length);
#elif defined(V8_HOST_ARCH_ARM64)
#else
// The code below assumes user space cache operations are allowed. The goal
// of this routine is to make sure the code generated is visible to the I
// side of the CPU.
@ -109,6 +110,7 @@ void CpuFeatures::FlushICache(void* address, size_t length) {
// move this code before the code is generated.
: "cc", "memory"
); // NOLINT
#endif // V8_OS_WIN
#endif // V8_HOST_ARCH_ARM64
}