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Update load_rax and store_rax to support X32

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R=verwaest@chromium.org

Review URL: https://codereview.chromium.org/103843002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@18640 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
haitao.feng@intel.com 2014-01-16 11:35:30 +00:00
parent e3fdf3f4e7
commit 95b0c6ebcf
1 changed files with 26 additions and 6 deletions
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20
src/x64/assembler-x64.cc
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@ -1305,9 +1305,19 @@ void Assembler::leal(Register dst, const Operand& src) {
void Assembler::load_rax(void* value, RelocInfo::Mode mode) {
EnsureSpace ensure_space(this);
if (kPointerSize == kInt64Size) {
emit(0x48); // REX.W
emit(0xA1);
emitp(value, mode);
} else {
ASSERT(kPointerSize == kInt32Size);
emit(0xA1);
emitp(value, mode);
// In 64-bit mode, need to zero extend the operand to 8 bytes.
// See 2.2.1.4 in Intel64 and IA32 Architectures Software
// Developer's Manual Volume 2.
emitl(0);
}
}
@ -1888,9 +1898,19 @@ void Assembler::xchgl(Register dst, Register src) {
void Assembler::store_rax(void* dst, RelocInfo::Mode mode) {
EnsureSpace ensure_space(this);
if (kPointerSize == kInt64Size) {
emit(0x48); // REX.W
emit(0xA3);
emitp(dst, mode);
} else {
ASSERT(kPointerSize == kInt32Size);
emit(0xA3);
emitp(dst, mode);
// In 64-bit mode, need to zero extend the operand to 8 bytes.
// See 2.2.1.4 in Intel64 and IA32 Architectures Software
// Developer's Manual Volume 2.
emitl(0);
}
}