AuroraMiddleware/v8
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[x64] Use macro list to define AVX instructions

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We were already using it to define the SSE instructions.

Bug: v8:10933
Change-Id: I8c70c027449ee8b0d00a06298087310ced11cafc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2470200
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70516}
This commit is contained in:
Ng Zhi An 2020-10-13 20:28:33 -07:00 committed by Commit Bot
parent 86b458396f
commit 96b7d98a92
2 changed files with 18 additions and 35 deletions
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50
src/codegen/x64/assembler-x64.h
View File

@ -1065,11 +1065,11 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
#define DECLARE_SSE4_EXTRACT_INSTRUCTION(instruction, prefix, escape1, \
escape2, opcode) \
void instruction(Register dst, XMMRegister src, int8_t imm8) { \
void instruction(Register dst, XMMRegister src, uint8_t imm8) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
imm8); \
} \
void instruction(Operand dst, XMMRegister src, int8_t imm8) { \
void instruction(Operand dst, XMMRegister src, uint8_t imm8) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
imm8); \
}
@ -1138,6 +1138,20 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE4_PMOV_AVX_INSTRUCTION)
#undef DECLARE_SSE4_PMOV_AVX_INSTRUCTION
#define DECLARE_AVX_INSTRUCTION(instruction, prefix, escape1, escape2, opcode) \
void v##instruction(Register dst, XMMRegister src, uint8_t imm8) { \
XMMRegister idst = XMMRegister::from_code(dst.code()); \
vinstr(0x##opcode, src, xmm0, idst, k##prefix, k##escape1##escape2, kW0); \
emit(imm8); \
} \
void v##instruction(Operand dst, XMMRegister src, uint8_t imm8) { \
vinstr(0x##opcode, src, xmm0, dst, k##prefix, k##escape1##escape2, kW0); \
emit(imm8); \
}
SSE4_EXTRACT_INSTRUCTION_LIST(DECLARE_AVX_INSTRUCTION)
#undef DECLARE_AVX_INSTRUCTION
void movd(XMMRegister dst, Register src);
void movd(XMMRegister dst, Operand src);
void movd(Register dst, XMMRegister src);
@ -1533,38 +1547,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
vinstr(0x21, dst, src1, src2, k66, k0F3A, kWIG);
emit(imm8);
}
void vextractps(Register dst, XMMRegister src, int8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x17, src, xmm0, idst, k66, k0F3A, kWIG);
emit(imm8);
}
void vpextrb(Register dst, XMMRegister src, uint8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x14, src, xmm0, idst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrb(Operand dst, XMMRegister src, uint8_t imm8) {
vinstr(0x14, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrw(Register dst, XMMRegister src, uint8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0xc5, idst, xmm0, src, k66, k0F, kW0);
emit(imm8);
}
void vpextrw(Operand dst, XMMRegister src, uint8_t imm8) {
vinstr(0x15, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrd(Register dst, XMMRegister src, uint8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x16, src, xmm0, idst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrd(Operand dst, XMMRegister src, uint8_t imm8) {
vinstr(0x16, src, xmm0, dst, k66, k0F3A, kW0);
emit(imm8);
}
void vpextrq(Register dst, XMMRegister src, int8_t imm8) {
XMMRegister idst = XMMRegister::from_code(dst.code());
vinstr(0x16, src, xmm0, idst, k66, k0F3A, kW1);

3
src/compiler/backend/x64/code-generator-x64.cc
View File

@ -2496,7 +2496,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kX64F32x4ExtractLane: {
__ Extractps(kScratchRegister, i.InputSimd128Register(0), i.InputInt8(1));
__ Extractps(kScratchRegister, i.InputSimd128Register(0),
i.InputUint8(1));
__ Movd(i.OutputDoubleRegister(), kScratchRegister);
break;
}