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[mips][wasm-simd] Remove i8x16.mul

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Port: 47ffa7a5fa

Bug: v8:6020
Change-Id: I4ae6261828b27f88553781a93d8557b6b685c217
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2719811
Auto-Submit: Liu yu <liuyu@loongson.cn>
Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#73069}
This commit is contained in:
Liu Yu 2021-02-26 15:11:12 +08:00 committed by Commit Bot
parent 19e8abbb56
commit 98cbf95368
10 changed files with 0 additions and 28 deletions
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6
src/compiler/backend/mips/code-generator-mips.cc
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@ -3006,12 +3006,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMipsI8x16Mul: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ mulv_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI8x16MaxS: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ max_s_b(i.OutputSimd128Register(), i.InputSimd128Register(0),

1
src/compiler/backend/mips/instruction-codes-mips.h
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@ -290,7 +290,6 @@ namespace compiler {
V(MipsI8x16AddSatS) \
V(MipsI8x16Sub) \
V(MipsI8x16SubSatS) \
V(MipsI8x16Mul) \
V(MipsI8x16MaxS) \
V(MipsI8x16MinS) \
V(MipsI8x16Eq) \

1
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -229,7 +229,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsI8x16MaxU:
case kMipsI8x16MinS:
case kMipsI8x16MinU:
case kMipsI8x16Mul:
case kMipsI8x16Ne:
case kMipsI8x16Neg:
case kMipsI8x16ReplaceLane:

1
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2275,7 +2275,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16Sub, kMipsI8x16Sub) \
V(I8x16SubSatS, kMipsI8x16SubSatS) \
V(I8x16SubSatU, kMipsI8x16SubSatU) \
V(I8x16Mul, kMipsI8x16Mul) \
V(I8x16MaxS, kMipsI8x16MaxS) \
V(I8x16MinS, kMipsI8x16MinS) \
V(I8x16MaxU, kMipsI8x16MaxU) \

6
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -3163,12 +3163,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMips64I8x16Mul: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ mulv_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I8x16MaxS: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ max_s_b(i.OutputSimd128Register(), i.InputSimd128Register(0),

1
src/compiler/backend/mips64/instruction-codes-mips64.h
View File

@ -312,7 +312,6 @@ namespace compiler {
V(Mips64I8x16AddSatS) \
V(Mips64I8x16Sub) \
V(Mips64I8x16SubSatS) \
V(Mips64I8x16Mul) \
V(Mips64I8x16MaxS) \
V(Mips64I8x16MinS) \
V(Mips64I8x16Eq) \

1
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -248,7 +248,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64I8x16MaxU:
case kMips64I8x16MinS:
case kMips64I8x16MinU:
case kMips64I8x16Mul:
case kMips64I8x16Ne:
case kMips64I8x16Neg:
case kMips64I8x16ReplaceLane:

1
src/compiler/backend/mips64/instruction-selector-mips64.cc
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@ -2995,7 +2995,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16Sub, kMips64I8x16Sub) \
V(I8x16SubSatS, kMips64I8x16SubSatS) \
V(I8x16SubSatU, kMips64I8x16SubSatU) \
V(I8x16Mul, kMips64I8x16Mul) \
V(I8x16MaxS, kMips64I8x16MaxS) \
V(I8x16MinS, kMips64I8x16MinS) \
V(I8x16MaxU, kMips64I8x16MaxU) \

5
src/wasm/baseline/mips/liftoff-assembler-mips.h
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@ -2095,11 +2095,6 @@ void LiftoffAssembler::emit_i8x16_sub_sat_u(LiftoffRegister dst,
bailout(kSimd, "emit_i8x16_sub_sat_u");
}
void LiftoffAssembler::emit_i8x16_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "emit_i8x16_mul");
}
void LiftoffAssembler::emit_i8x16_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {

5
src/wasm/baseline/mips64/liftoff-assembler-mips64.h
View File

@ -2073,11 +2073,6 @@ void LiftoffAssembler::emit_i8x16_sub_sat_u(LiftoffRegister dst,
subs_u_b(dst.fp().toW(), lhs.fp().toW(), rhs.fp().toW());
}
void LiftoffAssembler::emit_i8x16_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
mulv_b(dst.fp().toW(), lhs.fp().toW(), rhs.fp().toW());
}
void LiftoffAssembler::emit_i8x16_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {