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Fixed random style violations.

Browse Source 
Review URL: http://codereview.chromium.org/574009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3801 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
sgjesse@chromium.org 2010-02-04 21:32:02 +00:00
parent 4bf7a6c037
commit 9b4312fd76
10 changed files with 168 additions and 174 deletions
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156
src/arm/assembler-arm.cc
View File

@ -264,9 +264,9 @@ MemOperand::MemOperand(Register rn, Register rm,
// -----------------------------------------------------------------------------
// Implementation of Assembler
// Implementation of Assembler.
// Instruction encoding bits
// Instruction encoding bits.
enum {
H = 1 << 5, // halfword (or byte)
S6 = 1 << 6, // signed (or unsigned)
@ -299,14 +299,14 @@ enum {
B26 = 1 << 26,
B27 = 1 << 27,
// Instruction bit masks
// Instruction bit masks.
RdMask = 15 << 12, // in str instruction
CondMask = 15 << 28,
CoprocessorMask = 15 << 8,
OpCodeMask = 15 << 21, // in data-processing instructions
Imm24Mask = (1 << 24) - 1,
Off12Mask = (1 << 12) - 1,
// Reserved condition
// Reserved condition.
nv = 15 << 28
};
@ -327,13 +327,13 @@ const Instr kMovLrPc = al | 13*B21 | pc.code() | lr.code() * B12;
// ldr pc, [pc, #XXX]
const Instr kLdrPCPattern = al | B26 | L | pc.code() * B16;
// spare_buffer_
// Spare buffer.
static const int kMinimalBufferSize = 4*KB;
static byte* spare_buffer_ = NULL;
Assembler::Assembler(void* buffer, int buffer_size) {
if (buffer == NULL) {
// do our own buffer management
// Do our own buffer management.
if (buffer_size <= kMinimalBufferSize) {
buffer_size = kMinimalBufferSize;
@ -351,14 +351,14 @@ Assembler::Assembler(void* buffer, int buffer_size) {
own_buffer_ = true;
} else {
// use externally provided buffer instead
// Use externally provided buffer instead.
ASSERT(buffer_size > 0);
buffer_ = static_cast<byte*>(buffer);
buffer_size_ = buffer_size;
own_buffer_ = false;
}
// setup buffer pointers
// Setup buffer pointers.
ASSERT(buffer_ != NULL);
pc_ = buffer_;
reloc_info_writer.Reposition(buffer_ + buffer_size, pc_);
@ -386,11 +386,11 @@ Assembler::~Assembler() {
void Assembler::GetCode(CodeDesc* desc) {
// emit constant pool if necessary
// Emit constant pool if necessary.
CheckConstPool(true, false);
ASSERT(num_prinfo_ == 0);
// setup desc
// Setup code descriptor.
desc->buffer = buffer_;
desc->buffer_size = buffer_size_;
desc->instr_size = pc_offset();
@ -539,7 +539,7 @@ void Assembler::bind_to(Label* L, int pos) {
void Assembler::link_to(Label* L, Label* appendix) {
if (appendix->is_linked()) {
if (L->is_linked()) {
// append appendix to L's list
// Append appendix to L's list.
int fixup_pos;
int link = L->pos();
do {
@ -549,7 +549,7 @@ void Assembler::link_to(Label* L, Label* appendix) {
ASSERT(link == kEndOfChain);
target_at_put(fixup_pos, appendix->pos());
} else {
// L is empty, simply use appendix
// L is empty, simply use appendix.
*L = *appendix;
}
}
@ -575,12 +575,12 @@ void Assembler::next(Label* L) {
}
// Low-level code emission routines depending on the addressing mode
// Low-level code emission routines depending on the addressing mode.
static bool fits_shifter(uint32_t imm32,
uint32_t* rotate_imm,
uint32_t* immed_8,
Instr* instr) {
// imm32 must be unsigned
// imm32 must be unsigned.
for (int rot = 0; rot < 16; rot++) {
uint32_t imm8 = (imm32 << 2*rot) | (imm32 >> (32 - 2*rot));
if ((imm8 <= 0xff)) {
@ -589,7 +589,7 @@ static bool fits_shifter(uint32_t imm32,
return true;
}
}
// if the opcode is mov or mvn and if ~imm32 fits, change the opcode
// If the opcode is mov or mvn and if ~imm32 fits, change the opcode.
if (instr != NULL && (*instr & 0xd*B21) == 0xd*B21) {
if (fits_shifter(~imm32, rotate_imm, immed_8, NULL)) {
*instr ^= 0x2*B21;
@ -626,7 +626,7 @@ void Assembler::addrmod1(Instr instr,
CheckBuffer();
ASSERT((instr & ~(CondMask | OpCodeMask | S)) == 0);
if (!x.rm_.is_valid()) {
// immediate
// Immediate.
uint32_t rotate_imm;
uint32_t immed_8;
if (MustUseIp(x.rmode_) ||
@ -634,7 +634,7 @@ void Assembler::addrmod1(Instr instr,
// The immediate operand cannot be encoded as a shifter operand, so load
// it first to register ip and change the original instruction to use ip.
// However, if the original instruction is a 'mov rd, x' (not setting the
// condition code), then replace it with a 'ldr rd, [pc]'
// condition code), then replace it with a 'ldr rd, [pc]'.
RecordRelocInfo(x.rmode_, x.imm32_);
CHECK(!rn.is(ip)); // rn should never be ip, or will be trashed
Condition cond = static_cast<Condition>(instr & CondMask);
@ -648,16 +648,16 @@ void Assembler::addrmod1(Instr instr,
}
instr |= I | rotate_imm*B8 | immed_8;
} else if (!x.rs_.is_valid()) {
// immediate shift
// Immediate shift.
instr |= x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
} else {
// register shift
// Register shift.
ASSERT(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));
instr |= x.rs_.code()*B8 | x.shift_op_ | B4 | x.rm_.code();
}
emit(instr | rn.code()*B16 | rd.code()*B12);
if (rn.is(pc) || x.rm_.is(pc))
// block constant pool emission for one instruction after reading pc
// Block constant pool emission for one instruction after reading pc.
BlockConstPoolBefore(pc_offset() + kInstrSize);
}
@ -666,15 +666,15 @@ void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {
ASSERT((instr & ~(CondMask | B | L)) == B26);
int am = x.am_;
if (!x.rm_.is_valid()) {
// immediate offset
// Immediate offset.
int offset_12 = x.offset_;
if (offset_12 < 0) {
offset_12 = -offset_12;
am ^= U;
}
if (!is_uint12(offset_12)) {
// immediate offset cannot be encoded, load it first to register ip
// rn (and rd in a load) should never be ip, or will be trashed
// Immediate offset cannot be encoded, load it first to register ip
// rn (and rd in a load) should never be ip, or will be trashed.
ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
mov(ip, Operand(x.offset_), LeaveCC,
static_cast<Condition>(instr & CondMask));
@ -684,9 +684,9 @@ void Assembler::addrmod2(Instr instr, Register rd, const MemOperand& x) {
ASSERT(offset_12 >= 0); // no masking needed
instr |= offset_12;
} else {
// register offset (shift_imm_ and shift_op_ are 0) or scaled
// Register offset (shift_imm_ and shift_op_ are 0) or scaled
// register offset the constructors make sure than both shift_imm_
// and shift_op_ are initialized
// and shift_op_ are initialized.
ASSERT(!x.rm_.is(pc));
instr |= B25 | x.shift_imm_*B7 | x.shift_op_ | x.rm_.code();
}
@ -700,15 +700,15 @@ void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {
ASSERT(x.rn_.is_valid());
int am = x.am_;
if (!x.rm_.is_valid()) {
// immediate offset
// Immediate offset.
int offset_8 = x.offset_;
if (offset_8 < 0) {
offset_8 = -offset_8;
am ^= U;
}
if (!is_uint8(offset_8)) {
// immediate offset cannot be encoded, load it first to register ip
// rn (and rd in a load) should never be ip, or will be trashed
// Immediate offset cannot be encoded, load it first to register ip
// rn (and rd in a load) should never be ip, or will be trashed.
ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
mov(ip, Operand(x.offset_), LeaveCC,
static_cast<Condition>(instr & CondMask));
@ -718,15 +718,15 @@ void Assembler::addrmod3(Instr instr, Register rd, const MemOperand& x) {
ASSERT(offset_8 >= 0); // no masking needed
instr |= B | (offset_8 >> 4)*B8 | (offset_8 & 0xf);
} else if (x.shift_imm_ != 0) {
// scaled register offset not supported, load index first
// rn (and rd in a load) should never be ip, or will be trashed
// Scaled register offset not supported, load index first
// rn (and rd in a load) should never be ip, or will be trashed.
ASSERT(!x.rn_.is(ip) && ((instr & L) == L || !rd.is(ip)));
mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC,
static_cast<Condition>(instr & CondMask));
addrmod3(instr, rd, MemOperand(x.rn_, ip, x.am_));
return;
} else {
// register offset
// Register offset.
ASSERT((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback
instr |= x.rm_.code();
}
@ -744,7 +744,7 @@ void Assembler::addrmod4(Instr instr, Register rn, RegList rl) {
void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) {
// unindexed addressing is not encoded by this function
// Unindexed addressing is not encoded by this function.
ASSERT_EQ((B27 | B26),
(instr & ~(CondMask | CoprocessorMask | P | U | N | W | L)));
ASSERT(x.rn_.is_valid() && !x.rm_.is_valid());
@ -759,7 +759,7 @@ void Assembler::addrmod5(Instr instr, CRegister crd, const MemOperand& x) {
ASSERT(is_uint8(offset_8)); // unsigned word offset must fit in a byte
ASSERT((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
// post-indexed addressing requires W == 1; different than in addrmod2/3
// Post-indexed addressing requires W == 1; different than in addrmod2/3.
if ((am & P) == 0)
am |= W;
@ -782,7 +782,7 @@ int Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {
}
// Block the emission of the constant pool, since the branch instruction must
// be emitted at the pc offset recorded by the label
// be emitted at the pc offset recorded by the label.
BlockConstPoolBefore(pc_offset() + kInstrSize);
return target_pos - (pc_offset() + kPcLoadDelta);
}
@ -804,7 +804,7 @@ void Assembler::label_at_put(Label* L, int at_offset) {
}
// Branch instructions
// Branch instructions.
void Assembler::b(int branch_offset, Condition cond) {
ASSERT((branch_offset & 3) == 0);
int imm24 = branch_offset >> 2;
@ -812,7 +812,7 @@ void Assembler::b(int branch_offset, Condition cond) {
emit(cond | B27 | B25 | (imm24 & Imm24Mask));
if (cond == al)
// dead code is a good location to emit the constant pool
// Dead code is a good location to emit the constant pool.
CheckConstPool(false, false);
}
@ -849,7 +849,7 @@ void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t
}
// Data-processing instructions
// Data-processing instructions.
void Assembler::and_(Register dst, Register src1, const Operand& src2,
SBit s, Condition cond) {
addrmod1(cond | 0*B21 | s, src1, dst, src2);
@ -886,7 +886,7 @@ void Assembler::add(Register dst, Register src1, const Operand& src2,
if (FLAG_push_pop_elimination &&
last_bound_pos_ <= (pc_offset() - pattern_size) &&
reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
// pattern
// Pattern.
instr_at(pc_ - 1 * kInstrSize) == kPopInstruction &&
(instr_at(pc_ - 2 * kInstrSize) & ~RdMask) == kPushRegPattern) {
pc_ -= 2 * kInstrSize;
@ -960,7 +960,7 @@ void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
}
// Multiply instructions
// Multiply instructions.
void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
SBit s, Condition cond) {
ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
@ -1029,7 +1029,7 @@ void Assembler::umull(Register dstL,
}
// Miscellaneous arithmetic instructions
// Miscellaneous arithmetic instructions.
void Assembler::clz(Register dst, Register src, Condition cond) {
// v5 and above.
ASSERT(!dst.is(pc) && !src.is(pc));
@ -1038,7 +1038,7 @@ void Assembler::clz(Register dst, Register src, Condition cond) {
}
// Status register access instructions
// Status register access instructions.
void Assembler::mrs(Register dst, SRegister s, Condition cond) {
ASSERT(!dst.is(pc));
emit(cond | B24 | s | 15*B16 | dst.code()*B12);
@ -1050,12 +1050,12 @@ void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
ASSERT(fields >= B16 && fields < B20); // at least one field set
Instr instr;
if (!src.rm_.is_valid()) {
// immediate
// Immediate.
uint32_t rotate_imm;
uint32_t immed_8;
if (MustUseIp(src.rmode_) ||
!fits_shifter(src.imm32_, &rotate_imm, &immed_8, NULL)) {
// immediate operand cannot be encoded, load it first to register ip
// Immediate operand cannot be encoded, load it first to register ip.
RecordRelocInfo(src.rmode_, src.imm32_);
ldr(ip, MemOperand(pc, 0), cond);
msr(fields, Operand(ip), cond);
@ -1070,7 +1070,7 @@ void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
}
// Load/Store instructions
// Load/Store instructions.
void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
if (dst.is(pc)) {
WriteRecordedPositions();
@ -1085,7 +1085,7 @@ void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
if (FLAG_push_pop_elimination &&
last_bound_pos_ <= (pc_offset() - pattern_size) &&
reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
// pattern
// Pattern.
instr_at(pc_ - 1 * kInstrSize) == (kPopRegPattern | dst.code() * B12) &&
instr_at(pc_ - 2 * kInstrSize) == (kPushRegPattern | dst.code() * B12)) {
pc_ -= 2 * kInstrSize;
@ -1106,6 +1106,7 @@ void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
if (FLAG_push_pop_elimination &&
last_bound_pos_ <= (pc_offset() - pattern_size) &&
reloc_info_writer.last_pc() <= (pc_ - pattern_size) &&
// Pattern.
instr_at(pc_ - 1 * kInstrSize) == (kPushRegPattern | src.code() * B12) &&
instr_at(pc_ - 2 * kInstrSize) == kPopInstruction) {
pc_ -= 2 * kInstrSize;
@ -1147,17 +1148,17 @@ void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
}
// Load/Store multiple instructions
// Load/Store multiple instructions.
void Assembler::ldm(BlockAddrMode am,
Register base,
RegList dst,
Condition cond) {
// ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable
// ABI stack constraint: ldmxx base, {..sp..} base != sp is not restartable.
ASSERT(base.is(sp) || (dst & sp.bit()) == 0);
addrmod4(cond | B27 | am | L, base, dst);
// emit the constant pool after a function return implemented by ldm ..{..pc}
// Emit the constant pool after a function return implemented by ldm ..{..pc}.
if (cond == al && (dst & pc.bit()) != 0) {
// There is a slight chance that the ldm instruction was actually a call,
// in which case it would be wrong to return into the constant pool; we
@ -1177,7 +1178,7 @@ void Assembler::stm(BlockAddrMode am,
}
// Semaphore instructions
// Semaphore instructions.
void Assembler::swp(Register dst, Register src, Register base, Condition cond) {
ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc));
ASSERT(!dst.is(base) && !src.is(base));
@ -1197,7 +1198,7 @@ void Assembler::swpb(Register dst,
}
// Exception-generating instructions and debugging support
// Exception-generating instructions and debugging support.
void Assembler::stop(const char* msg) {
#if !defined(__arm__)
// The simulator handles these special instructions and stops execution.
@ -1222,7 +1223,7 @@ void Assembler::swi(uint32_t imm24, Condition cond) {
}
// Coprocessor instructions
// Coprocessor instructions.
void Assembler::cdp(Coprocessor coproc,
int opcode_1,
CRegister crd,
@ -1307,7 +1308,7 @@ void Assembler::ldc(Coprocessor coproc,
int option,
LFlag l,
Condition cond) {
// unindexed addressing
// Unindexed addressing.
ASSERT(is_uint8(option));
emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 |
coproc*B8 | (option & 255));
@ -1346,7 +1347,7 @@ void Assembler::stc(Coprocessor coproc,
int option,
LFlag l,
Condition cond) {
// unindexed addressing
// Unindexed addressing.
ASSERT(is_uint8(option));
emit(cond | B27 | B26 | U | l | rn.code()*B16 | crd.code()*B12 |
coproc*B8 | (option & 255));
@ -1464,7 +1465,7 @@ void Assembler::vcvt(const DwVfpRegister dst,
const Condition cond) {
// Dd = Sm (integer in Sm converted to IEEE 64-bit doubles in Dd).
// Instruction details available in ARM DDI 0406A, A8-576.
// cond(31-28) | 11101(27-23)| D=?(22) | 11(21-20) | 1(19) |opc2=000(18-16) |
// cond(31-28) | 11101(27-23)| D=?(22) | 11(21-20) | 1(19) | opc2=000(18-16) |
// Vd(15-12) | 101(11-9) | sz(8)=1 | op(7)=1 | 1(6) | M=?(5) | 0(4) | Vm(3-0)
ASSERT(CpuFeatures::IsEnabled(VFP3));
emit(cond | 0xE*B24 | B23 | 0x3*B20 | B19 |
@ -1571,14 +1572,14 @@ void Assembler::vmrs(Register dst, Condition cond) {
}
// Pseudo instructions
// Pseudo instructions.
void Assembler::lea(Register dst,
const MemOperand& x,
SBit s,
Condition cond) {
int am = x.am_;
if (!x.rm_.is_valid()) {
// immediate offset
// Immediate offset.
if ((am & P) == 0) // post indexing
mov(dst, Operand(x.rn_), s, cond);
else if ((am & U) == 0) // negative indexing
@ -1612,7 +1613,7 @@ void Assembler::BlockConstPoolFor(int instructions) {
}
// Debugging
// Debugging.
void Assembler::RecordJSReturn() {
WriteRecordedPositions();
CheckBuffer();
@ -1665,7 +1666,7 @@ void Assembler::WriteRecordedPositions() {
void Assembler::GrowBuffer() {
if (!own_buffer_) FATAL("external code buffer is too small");
// compute new buffer size
// Compute new buffer size.
CodeDesc desc; // the new buffer
if (buffer_size_ < 4*KB) {
desc.buffer_size = 4*KB;
@ -1676,20 +1677,20 @@ void Assembler::GrowBuffer() {
}
CHECK_GT(desc.buffer_size, 0); // no overflow
// setup new buffer
// Setup new buffer.
desc.buffer = NewArray<byte>(desc.buffer_size);
desc.instr_size = pc_offset();
desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
// copy the data
// Copy the data.
int pc_delta = desc.buffer - buffer_;
int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
memmove(desc.buffer, buffer_, desc.instr_size);
memmove(reloc_info_writer.pos() + rc_delta,
reloc_info_writer.pos(), desc.reloc_size);
// switch buffers
// Switch buffers.
DeleteArray(buffer_);
buffer_ = desc.buffer;
buffer_size_ = desc.buffer_size;
@ -1697,11 +1698,11 @@ void Assembler::GrowBuffer() {
reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
reloc_info_writer.last_pc() + pc_delta);
// none of our relocation types are pc relative pointing outside the code
// None of our relocation types are pc relative pointing outside the code
// buffer nor pc absolute pointing inside the code buffer, so there is no need
// to relocate any emitted relocation entries
// to relocate any emitted relocation entries.
// relocate pending relocation entries
// Relocate pending relocation entries.
for (int i = 0; i < num_prinfo_; i++) {
RelocInfo& rinfo = prinfo_[i];
ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
@ -1716,16 +1717,16 @@ void Assembler::GrowBuffer() {
void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
RelocInfo rinfo(pc_, rmode, data); // we do not try to reuse pool constants
if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::STATEMENT_POSITION) {
// Adjust code for new modes
// Adjust code for new modes.
ASSERT(RelocInfo::IsJSReturn(rmode)
|| RelocInfo::IsComment(rmode)
|| RelocInfo::IsPosition(rmode));
// these modes do not need an entry in the constant pool
// These modes do not need an entry in the constant pool.
} else {
ASSERT(num_prinfo_ < kMaxNumPRInfo);
prinfo_[num_prinfo_++] = rinfo;
// Make sure the constant pool is not emitted in place of the next
// instruction for which we just recorded relocation info
// instruction for which we just recorded relocation info.
BlockConstPoolBefore(pc_offset() + kInstrSize);
}
if (rinfo.rmode() != RelocInfo::NONE) {
@ -1752,7 +1753,7 @@ void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
// blocked for a specific range.
next_buffer_check_ = pc_offset() + kCheckConstInterval;
// There is nothing to do if there are no pending relocation info entries
// There is nothing to do if there are no pending relocation info entries.
if (num_prinfo_ == 0) return;
// We emit a constant pool at regular intervals of about kDistBetweenPools
@ -1778,10 +1779,11 @@ void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
// no_const_pool_before_, which is checked here. Also, recursive calls to
// CheckConstPool are blocked by no_const_pool_before_.
if (pc_offset() < no_const_pool_before_) {
// Emission is currently blocked; make sure we try again as soon as possible
// Emission is currently blocked; make sure we try again as soon as
// possible.
next_buffer_check_ = no_const_pool_before_;
// Something is wrong if emission is forced and blocked at the same time
// Something is wrong if emission is forced and blocked at the same time.
ASSERT(!force_emit);
return;
}
@ -1795,23 +1797,23 @@ void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
jump_instr + kInstrSize + num_prinfo_*(kInstrSize + kMaxRelocSize);
while (buffer_space() <= (max_needed_space + kGap)) GrowBuffer();
// Block recursive calls to CheckConstPool
// Block recursive calls to CheckConstPool.
BlockConstPoolBefore(pc_offset() + jump_instr + kInstrSize +
num_prinfo_*kInstrSize);
// Don't bother to check for the emit calls below.
next_buffer_check_ = no_const_pool_before_;
// Emit jump over constant pool if necessary
// Emit jump over constant pool if necessary.
Label after_pool;
if (require_jump) b(&after_pool);
RecordComment("[ Constant Pool");
// Put down constant pool marker
// "Undefined instruction" as specified by A3.1 Instruction set encoding
// Put down constant pool marker "Undefined instruction" as specified by
// A3.1 Instruction set encoding.
emit(0x03000000 | num_prinfo_);
// Emit constant pool entries
// Emit constant pool entries.
for (int i = 0; i < num_prinfo_; i++) {
RelocInfo& rinfo = prinfo_[i];
ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
@ -1819,8 +1821,8 @@ void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
rinfo.rmode() != RelocInfo::STATEMENT_POSITION);
Instr instr = instr_at(rinfo.pc());
// Instruction to patch must be a ldr/str [pc, #offset]
// P and U set, B and W clear, Rn == pc, offset12 still 0
// Instruction to patch must be a ldr/str [pc, #offset].
// P and U set, B and W clear, Rn == pc, offset12 still 0.
ASSERT((instr & (7*B25 | P | U | B | W | 15*B16 | Off12Mask)) ==
(2*B25 | P | U | pc.code()*B16));
int delta = pc_ - rinfo.pc() - 8;

4
src/arm/assembler-arm.h
View File

@ -80,7 +80,7 @@ struct Register {
return 1 << code_;
}
// (unfortunately we can't make this private in a struct)
// Unfortunately we can't make this private in a struct.
int code_;
};
@ -205,7 +205,7 @@ struct CRegister {
return 1 << code_;
}
// (unfortunately we can't make this private in a struct)
// Unfortunately we can't make this private in a struct.
int code_;
};

4
src/arm/assembler-thumb2.h
View File

@ -80,7 +80,7 @@ struct Register {
return 1 << code_;
}
// (unfortunately we can't make this private in a struct)
// Unfortunately we can't make this private in a struct.
int code_;
};
@ -205,7 +205,7 @@ struct CRegister {
return 1 << code_;
}
// (unfortunately we can't make this private in a struct)
// Unfortunately we can't make this private in a struct.
int code_;
};

22
src/arm/macro-assembler-arm.h
View File

@ -57,14 +57,7 @@ class MacroAssembler: public Assembler {
public:
MacroAssembler(void* buffer, int size);
// ---------------------------------------------------------------------------
// Low-level helpers for compiler
// Jump, Call, and Ret pseudo instructions implementing inter-working
private:
void Jump(intptr_t target, RelocInfo::Mode rmode, Condition cond = al);
void Call(intptr_t target, RelocInfo::Mode rmode, Condition cond = al);
public:
// Jump, Call, and Ret pseudo instructions implementing inter-working.
void Jump(Register target, Condition cond = al);
void Jump(byte* target, RelocInfo::Mode rmode, Condition cond = al);
void Jump(Handle<Code> code, RelocInfo::Mode rmode, Condition cond = al);
@ -394,11 +387,8 @@ class MacroAssembler: public Assembler {
Label* not_flat_ascii_strings);
private:
List<Unresolved> unresolved_;
bool generating_stub_;
bool allow_stub_calls_;
Handle<Object> code_object_; // This handle will be patched with the code
// object on installation.
void Jump(intptr_t target, RelocInfo::Mode rmode, Condition cond = al);
void Call(intptr_t target, RelocInfo::Mode rmode, Condition cond = al);
// Helper functions for generating invokes.
void InvokePrologue(const ParameterCount& expected,
@ -423,6 +413,12 @@ class MacroAssembler: public Assembler {
// Activation support.
void EnterFrame(StackFrame::Type type);
void LeaveFrame(StackFrame::Type type);
List<Unresolved> unresolved_;
bool generating_stub_;
bool allow_stub_calls_;
// This handle will be patched with the code object on installation.
Handle<Object> code_object_;
};

59
src/ia32/assembler-ia32.cc
View File

@ -267,7 +267,7 @@ bool Operand::is_reg(Register reg) const {
}
// -----------------------------------------------------------------------------
// Implementation of Assembler
// Implementation of Assembler.
// Emit a single byte. Must always be inlined.
#define EMIT(x) \
@ -278,12 +278,12 @@ bool Operand::is_reg(Register reg) const {
static void InitCoverageLog();
#endif
// spare_buffer_
// Spare buffer.
byte* Assembler::spare_buffer_ = NULL;
Assembler::Assembler(void* buffer, int buffer_size) {
if (buffer == NULL) {
// do our own buffer management
// Do our own buffer management.
if (buffer_size <= kMinimalBufferSize) {
buffer_size = kMinimalBufferSize;
@ -300,7 +300,7 @@ Assembler::Assembler(void* buffer, int buffer_size) {
buffer_size_ = buffer_size;
own_buffer_ = true;
} else {
// use externally provided buffer instead
// Use externally provided buffer instead.
ASSERT(buffer_size > 0);
buffer_ = static_cast<byte*>(buffer);
buffer_size_ = buffer_size;
@ -316,7 +316,7 @@ Assembler::Assembler(void* buffer, int buffer_size) {
}
#endif
// setup buffer pointers
// Setup buffer pointers.
ASSERT(buffer_ != NULL);
pc_ = buffer_;
reloc_info_writer.Reposition(buffer_ + buffer_size, pc_);
@ -344,11 +344,10 @@ Assembler::~Assembler() {
void Assembler::GetCode(CodeDesc* desc) {
// finalize code
// (at this point overflow() may be true, but the gap ensures that
// we are still not overlapping instructions and relocation info)
ASSERT(pc_ <= reloc_info_writer.pos()); // no overlap
// setup desc
// Finalize code (at this point overflow() may be true, but the gap ensures
// that we are still not overlapping instructions and relocation info).
ASSERT(pc_ <= reloc_info_writer.pos()); // No overlap.
// Setup code descriptor.
desc->buffer = buffer_;
desc->buffer_size = buffer_size_;
desc->instr_size = pc_offset();
@ -435,7 +434,7 @@ void Assembler::push(const Operand& src) {
void Assembler::pop(Register dst) {
ASSERT(reloc_info_writer.last_pc() != NULL);
if (FLAG_push_pop_elimination && (reloc_info_writer.last_pc() <= last_pc_)) {
// (last_pc_ != NULL) is rolled into the above check
// (last_pc_ != NULL) is rolled into the above check.
// If a last_pc_ is set, we need to make sure that there has not been any
// relocation information generated between the last instruction and this
// pop instruction.
@ -461,7 +460,7 @@ void Assembler::pop(Register dst) {
return;
} else if (instr == 0xff) { // push of an operand, convert to a move
byte op1 = last_pc_[1];
// Check if the operation is really a push
// Check if the operation is really a push.
if ((op1 & 0x38) == (6 << 3)) {
op1 = (op1 & ~0x38) | static_cast<byte>(dst.code() << 3);
last_pc_[0] = 0x8b;
@ -747,7 +746,7 @@ void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
ASSERT(CpuFeatures::IsEnabled(CMOV));
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode: 0f 40 + cc /r
// Opcode: 0f 40 + cc /r.
EMIT(0x0F);
EMIT(0x40 + cc);
emit_operand(dst, src);
@ -765,7 +764,7 @@ void Assembler::rep_movs() {
void Assembler::xchg(Register dst, Register src) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
if (src.is(eax) || dst.is(eax)) { // Single-byte encoding
if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
} else {
EMIT(0x87);
@ -1434,7 +1433,7 @@ void Assembler::bind_to(Label* L, int pos) {
if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
ASSERT(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
}
// relative address, relative to point after address
// Relative address, relative to point after address.
int imm32 = pos - (fixup_pos + sizeof(int32_t));
long_at_put(fixup_pos, imm32);
}
@ -1449,7 +1448,7 @@ void Assembler::link_to(Label* L, Label* appendix) {
last_pc_ = NULL;
if (appendix->is_linked()) {
if (L->is_linked()) {
// append appendix to L's list
// Append appendix to L's list.
Label p;
Label q = *L;
do {
@ -1462,7 +1461,7 @@ void Assembler::link_to(Label* L, Label* appendix) {
disp_at_put(&p, disp);
p.Unuse(); // to avoid assertion failure in ~Label
} else {
// L is empty, simply use appendix
// L is empty, simply use appendix.
*L = *appendix;
}
}
@ -1485,11 +1484,11 @@ void Assembler::call(Label* L) {
const int long_size = 5;
int offs = L->pos() - pc_offset();
ASSERT(offs <= 0);
// 1110 1000 #32-bit disp
// 1110 1000 #32-bit disp.
EMIT(0xE8);
emit(offs - long_size);
} else {
// 1110 1000 #32-bit disp
// 1110 1000 #32-bit disp.
EMIT(0xE8);
emit_disp(L, Displacement::OTHER);
}
@ -1532,16 +1531,16 @@ void Assembler::jmp(Label* L) {
int offs = L->pos() - pc_offset();
ASSERT(offs <= 0);
if (is_int8(offs - short_size)) {
// 1110 1011 #8-bit disp
// 1110 1011 #8-bit disp.
EMIT(0xEB);
EMIT((offs - short_size) & 0xFF);
} else {
// 1110 1001 #32-bit disp
// 1110 1001 #32-bit disp.
EMIT(0xE9);
emit(offs - long_size);
}
} else {
// 1110 1001 #32-bit disp
// 1110 1001 #32-bit disp.
EMIT(0xE9);
emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
}
@ -1611,7 +1610,7 @@ void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode, Hint hint) {
last_pc_ = pc_;
ASSERT((0 <= cc) && (cc < 16));
if (FLAG_emit_branch_hints && hint != no_hint) EMIT(hint);
// 0000 1111 1000 tttn #32-bit disp
// 0000 1111 1000 tttn #32-bit disp.
EMIT(0x0F);
EMIT(0x80 | cc);
emit(entry - (pc_ + sizeof(int32_t)), rmode);
@ -1629,7 +1628,7 @@ void Assembler::j(Condition cc, Handle<Code> code, Hint hint) {
}
// FPU instructions
// FPU instructions.
void Assembler::fld(int i) {
EnsureSpace ensure_space(this);
@ -2225,10 +2224,10 @@ void Assembler::WriteRecordedPositions() {
void Assembler::GrowBuffer() {
ASSERT(overflow()); // should not call this otherwise
ASSERT(overflow());
if (!own_buffer_) FATAL("external code buffer is too small");
// compute new buffer size
// Compute new buffer size.
CodeDesc desc; // the new buffer
if (buffer_size_ < 4*KB) {
desc.buffer_size = 4*KB;
@ -2242,7 +2241,7 @@ void Assembler::GrowBuffer() {
V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
}
// setup new buffer
// Setup new buffer.
desc.buffer = NewArray<byte>(desc.buffer_size);
desc.instr_size = pc_offset();
desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
@ -2253,14 +2252,14 @@ void Assembler::GrowBuffer() {
memset(desc.buffer, 0xCC, desc.buffer_size);
#endif
// copy the data
// Copy the data.
int pc_delta = desc.buffer - buffer_;
int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
memmove(desc.buffer, buffer_, desc.instr_size);
memmove(rc_delta + reloc_info_writer.pos(),
reloc_info_writer.pos(), desc.reloc_size);
// switch buffers
// Switch buffers.
if (spare_buffer_ == NULL && buffer_size_ == kMinimalBufferSize) {
spare_buffer_ = buffer_;
} else {
@ -2275,7 +2274,7 @@ void Assembler::GrowBuffer() {
reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
reloc_info_writer.last_pc() + pc_delta);
// relocate runtime entries
// Relocate runtime entries.
for (RelocIterator it(desc); !it.done(); it.next()) {
RelocInfo::Mode rmode = it.rinfo()->rmode();
if (rmode == RelocInfo::RUNTIME_ENTRY) {

2
src/ia32/assembler-ia32.h
View File

@ -77,7 +77,7 @@ struct Register {
return 1 << code_;
}
// (unfortunately we can't make this private in a struct)
// Unfortunately we can't make this private in a struct.
int code_;
};

4
src/ia32/macro-assembler-ia32.h
View File

@ -430,8 +430,8 @@ class MacroAssembler: public Assembler {
List<Unresolved> unresolved_;
bool generating_stub_;
bool allow_stub_calls_;
Handle<Object> code_object_; // This handle will be patched with the
// code object on installation.
// This handle will be patched with the code object on installation.
Handle<Object> code_object_;
// Helper functions for generating invokes.
void InvokePrologue(const ParameterCount& expected,

83
src/x64/assembler-x64.cc
View File

@ -265,7 +265,7 @@ Operand::Operand(Register base,
// -----------------------------------------------------------------------------
// Implementation of Assembler
// Implementation of Assembler.
#ifdef GENERATED_CODE_COVERAGE
static void InitCoverageLog();
@ -276,7 +276,7 @@ byte* Assembler::spare_buffer_ = NULL;
Assembler::Assembler(void* buffer, int buffer_size)
: code_targets_(100) {
if (buffer == NULL) {
// do our own buffer management
// Do our own buffer management.
if (buffer_size <= kMinimalBufferSize) {
buffer_size = kMinimalBufferSize;
@ -293,7 +293,7 @@ Assembler::Assembler(void* buffer, int buffer_size)
buffer_size_ = buffer_size;
own_buffer_ = true;
} else {
// use externally provided buffer instead
// Use externally provided buffer instead.
ASSERT(buffer_size > 0);
buffer_ = static_cast<byte*>(buffer);
buffer_size_ = buffer_size;
@ -309,7 +309,7 @@ Assembler::Assembler(void* buffer, int buffer_size)
}
#endif
// setup buffer pointers
// Setup buffer pointers.
ASSERT(buffer_ != NULL);
pc_ = buffer_;
reloc_info_writer.Reposition(buffer_ + buffer_size, pc_);
@ -337,11 +337,10 @@ Assembler::~Assembler() {
void Assembler::GetCode(CodeDesc* desc) {
// finalize code
// (at this point overflow() may be true, but the gap ensures that
// we are still not overlapping instructions and relocation info)
ASSERT(pc_ <= reloc_info_writer.pos()); // no overlap
// setup desc
// Finalize code (at this point overflow() may be true, but the gap ensures
// that we are still not overlapping instructions and relocation info).
ASSERT(pc_ <= reloc_info_writer.pos()); // No overlap.
// Setup code descriptor.
desc->buffer = buffer_;
desc->buffer_size = buffer_size_;
desc->instr_size = pc_offset();
@ -370,7 +369,7 @@ void Assembler::bind_to(Label* L, int pos) {
int current = L->pos();
int next = long_at(current);
while (next != current) {
// relative address, relative to point after address
// Relative address, relative to point after address.
int imm32 = pos - (current + sizeof(int32_t));
long_at_put(current, imm32);
current = next;
@ -390,10 +389,10 @@ void Assembler::bind(Label* L) {
void Assembler::GrowBuffer() {
ASSERT(buffer_overflow()); // should not call this otherwise
ASSERT(buffer_overflow());
if (!own_buffer_) FATAL("external code buffer is too small");
// compute new buffer size
// Compute new buffer size.
CodeDesc desc; // the new buffer
if (buffer_size_ < 4*KB) {
desc.buffer_size = 4*KB;
@ -407,7 +406,7 @@ void Assembler::GrowBuffer() {
V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
}
// setup new buffer
// Setup new buffer.
desc.buffer = NewArray<byte>(desc.buffer_size);
desc.instr_size = pc_offset();
desc.reloc_size =
@ -419,7 +418,7 @@ void Assembler::GrowBuffer() {
memset(desc.buffer, 0xCC, desc.buffer_size);
#endif
// copy the data
// Copy the data.
intptr_t pc_delta = desc.buffer - buffer_;
intptr_t rc_delta = (desc.buffer + desc.buffer_size) -
(buffer_ + buffer_size_);
@ -427,7 +426,7 @@ void Assembler::GrowBuffer() {
memmove(rc_delta + reloc_info_writer.pos(),
reloc_info_writer.pos(), desc.reloc_size);
// switch buffers
// Switch buffers.
if (spare_buffer_ == NULL && buffer_size_ == kMinimalBufferSize) {
spare_buffer_ = buffer_;
} else {
@ -442,7 +441,7 @@ void Assembler::GrowBuffer() {
reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
reloc_info_writer.last_pc() + pc_delta);
// relocate runtime entries
// Relocate runtime entries.
for (RelocIterator it(desc); !it.done(); it.next()) {
RelocInfo::Mode rmode = it.rinfo()->rmode();
if (rmode == RelocInfo::INTERNAL_REFERENCE) {
@ -472,7 +471,7 @@ void Assembler::emit_operand(int code, const Operand& adr) {
}
// Assembler Instruction implementations
// Assembler Instruction implementations.
void Assembler::arithmetic_op(byte opcode, Register reg, const Operand& op) {
EnsureSpace ensure_space(this);
@ -756,7 +755,7 @@ void Assembler::bts(const Operand& dst, Register src) {
void Assembler::call(Label* L) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// 1110 1000 #32-bit disp
// 1110 1000 #32-bit disp.
emit(0xE8);
if (L->is_bound()) {
int offset = L->pos() - pc_offset() - sizeof(int32_t);
@ -777,7 +776,7 @@ void Assembler::call(Label* L) {
void Assembler::call(Handle<Code> target, RelocInfo::Mode rmode) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// 1110 1000 #32-bit disp
// 1110 1000 #32-bit disp.
emit(0xE8);
emit_code_target(target, rmode);
}
@ -786,7 +785,7 @@ void Assembler::call(Handle<Code> target, RelocInfo::Mode rmode) {
void Assembler::call(Register adr) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode: FF /2 r64
// Opcode: FF /2 r64.
if (adr.high_bit()) {
emit_rex_64(adr);
}
@ -798,7 +797,7 @@ void Assembler::call(Register adr) {
void Assembler::call(const Operand& op) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode: FF /2 m64
// Opcode: FF /2 m64.
emit_rex_64(op);
emit(0xFF);
emit_operand(2, op);
@ -829,7 +828,7 @@ void Assembler::cmovq(Condition cc, Register dst, Register src) {
ASSERT(cc >= 0); // Use mov for unconditional moves.
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode: REX.W 0f 40 + cc /r
// Opcode: REX.W 0f 40 + cc /r.
emit_rex_64(dst, src);
emit(0x0f);
emit(0x40 + cc);
@ -846,7 +845,7 @@ void Assembler::cmovq(Condition cc, Register dst, const Operand& src) {
ASSERT(cc >= 0);
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode: REX.W 0f 40 + cc /r
// Opcode: REX.W 0f 40 + cc /r.
emit_rex_64(dst, src);
emit(0x0f);
emit(0x40 + cc);
@ -863,7 +862,7 @@ void Assembler::cmovl(Condition cc, Register dst, Register src) {
ASSERT(cc >= 0);
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode: 0f 40 + cc /r
// Opcode: 0f 40 + cc /r.
emit_optional_rex_32(dst, src);
emit(0x0f);
emit(0x40 + cc);
@ -880,7 +879,7 @@ void Assembler::cmovl(Condition cc, Register dst, const Operand& src) {
ASSERT(cc >= 0);
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode: 0f 40 + cc /r
// Opcode: 0f 40 + cc /r.
emit_optional_rex_32(dst, src);
emit(0x0f);
emit(0x40 + cc);
@ -1110,17 +1109,17 @@ void Assembler::j(Condition cc, Label* L) {
int offs = L->pos() - pc_offset();
ASSERT(offs <= 0);
if (is_int8(offs - short_size)) {
// 0111 tttn #8-bit disp
// 0111 tttn #8-bit disp.
emit(0x70 | cc);
emit((offs - short_size) & 0xFF);
} else {
// 0000 1111 1000 tttn #32-bit disp
// 0000 1111 1000 tttn #32-bit disp.
emit(0x0F);
emit(0x80 | cc);
emitl(offs - long_size);
}
} else if (L->is_linked()) {
// 0000 1111 1000 tttn #32-bit disp
// 0000 1111 1000 tttn #32-bit disp.
emit(0x0F);
emit(0x80 | cc);
emitl(L->pos());
@ -1142,7 +1141,7 @@ void Assembler::j(Condition cc,
EnsureSpace ensure_space(this);
last_pc_ = pc_;
ASSERT(is_uint4(cc));
// 0000 1111 1000 tttn #32-bit disp
// 0000 1111 1000 tttn #32-bit disp.
emit(0x0F);
emit(0x80 | cc);
emit_code_target(target, rmode);
@ -1156,21 +1155,21 @@ void Assembler::jmp(Label* L) {
int offs = L->pos() - pc_offset() - 1;
ASSERT(offs <= 0);
if (is_int8(offs - sizeof(int8_t))) {
// 1110 1011 #8-bit disp
// 1110 1011 #8-bit disp.
emit(0xEB);
emit((offs - sizeof(int8_t)) & 0xFF);
} else {
// 1110 1001 #32-bit disp
// 1110 1001 #32-bit disp.
emit(0xE9);
emitl(offs - sizeof(int32_t));
}
} else if (L->is_linked()) {
// 1110 1001 #32-bit disp
// 1110 1001 #32-bit disp.
emit(0xE9);
emitl(L->pos());
L->link_to(pc_offset() - sizeof(int32_t));
} else {
// 1110 1001 #32-bit disp
// 1110 1001 #32-bit disp.
ASSERT(L->is_unused());
emit(0xE9);
int32_t current = pc_offset();
@ -1183,7 +1182,7 @@ void Assembler::jmp(Label* L) {
void Assembler::jmp(Handle<Code> target, RelocInfo::Mode rmode) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// 1110 1001 #32-bit disp
// 1110 1001 #32-bit disp.
emit(0xE9);
emit_code_target(target, rmode);
}
@ -1192,7 +1191,7 @@ void Assembler::jmp(Handle<Code> target, RelocInfo::Mode rmode) {
void Assembler::jmp(Register target) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode FF/4 r64
// Opcode FF/4 r64.
if (target.high_bit()) {
emit_rex_64(target);
}
@ -1204,7 +1203,7 @@ void Assembler::jmp(Register target) {
void Assembler::jmp(const Operand& src) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
// Opcode FF/4 m64
// Opcode FF/4 m64.
emit_optional_rex_32(src);
emit(0xFF);
emit_operand(0x4, src);
@ -1413,10 +1412,8 @@ void Assembler::movq(const Operand& dst, Immediate value) {
}
/*
* Loads the ip-relative location of the src label into the target
* location (as a 32-bit offset sign extended to 64-bit).
*/
// Loads the ip-relative location of the src label into the target location
// (as a 32-bit offset sign extended to 64-bit).
void Assembler::movl(const Operand& dst, Label* src) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
@ -2006,7 +2003,7 @@ void Assembler::testq(Register dst, Immediate mask) {
}
// FPU instructions
// FPU instructions.
void Assembler::fld(int i) {
@ -2377,7 +2374,7 @@ void Assembler::emit_farith(int b1, int b2, int i) {
emit(b2 + i);
}
// SSE 2 operations
// SSE 2 operations.
void Assembler::movsd(const Operand& dst, XMMRegister src) {
EnsureSpace ensure_space(this);
@ -2527,7 +2524,7 @@ void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
}
// Relocation information implementations
// Relocation information implementations.
void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
ASSERT(rmode != RelocInfo::NONE);

4
src/x64/assembler-x64.h
View File

@ -113,8 +113,8 @@ struct Register {
return code_ & 0x7;
}
// (unfortunately we can't make this private in a struct when initializing
// by assignment.)
// Unfortunately we can't make this private in a struct when initializing
// by assignment.
int code_;
};

4
src/x64/macro-assembler-x64.h
View File

@ -712,8 +712,8 @@ class MacroAssembler: public Assembler {
List<Unresolved> unresolved_;
bool generating_stub_;
bool allow_stub_calls_;
Handle<Object> code_object_; // This handle will be patched with the code
// object on installation.
// This handle will be patched with the code object on installation.
Handle<Object> code_object_;
// Helper functions for generating invokes.
void InvokePrologue(const ParameterCount& expected,