Inline keyed load on ARM
This uses the same infrastructure as is used by the inlining of named property load. The code patching if the inlined code is simpler as the key is provided in a register os the only patching required is the map check directing the inlined code to the deferred code block or not. Review URL: http://codereview.chromium.org/1735007 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4510 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
sgjesse@chromium.org
parent
2e1298944f
commit
9b5ca37545
@ -800,10 +800,11 @@ void Assembler::b(int branch_offset, Condition cond) {
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ASSERT(is_int24(imm24));
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emit(cond | B27 | B25 | (imm24 & Imm24Mask));
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if (cond == al)
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if (cond == al) {
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// Dead code is a good location to emit the constant pool.
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CheckConstPool(false, false);
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}
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}
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void Assembler::bl(int branch_offset, Condition cond) {
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@ -3703,7 +3703,7 @@ void CodeGenerator::VisitCall(Call* node) {
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LoadAndSpill(property->obj());
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LoadAndSpill(property->key());
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EmitKeyedLoad(false);
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EmitKeyedLoad();
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frame_->Drop(); // key
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// Put the function below the receiver.
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if (property->is_synthetic()) {
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@ -5250,7 +5250,38 @@ void DeferredReferenceGetNamedValue::Generate() {
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__ Call(ic, RelocInfo::CODE_TARGET);
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// The call must be followed by a nop(1) instruction to indicate that the
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// in-object has been inlined.
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__ nop(NAMED_PROPERTY_LOAD_INLINED);
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__ nop(PROPERTY_LOAD_INLINED);
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// Block the constant pool for one more instruction after leaving this
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// constant pool block scope to include the branch instruction ending the
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// deferred code.
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__ BlockConstPoolFor(1);
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}
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}
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class DeferredReferenceGetKeyedValue: public DeferredCode {
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public:
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DeferredReferenceGetKeyedValue() {
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set_comment("[ DeferredReferenceGetKeyedValue");
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}
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virtual void Generate();
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};
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void DeferredReferenceGetKeyedValue::Generate() {
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__ DecrementCounter(&Counters::keyed_load_inline, 1, r1, r2);
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__ IncrementCounter(&Counters::keyed_load_inline_miss, 1, r1, r2);
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// The rest of the instructions in the deferred code must be together.
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{ Assembler::BlockConstPoolScope block_const_pool(masm_);
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// Call keyed load IC. It has all arguments on the stack.
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Handle<Code> ic(Builtins::builtin(Builtins::KeyedLoadIC_Initialize));
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__ Call(ic, RelocInfo::CODE_TARGET);
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// The call must be followed by a nop instruction to indicate that the
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// keyed load has been inlined.
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__ nop(PROPERTY_LOAD_INLINED);
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// Block the constant pool for one more instruction after leaving this
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// constant pool block scope to include the branch instruction ending the
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@ -5269,7 +5300,7 @@ void CodeGenerator::EmitNamedLoad(Handle<String> name, bool is_contextual) {
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? RelocInfo::CODE_TARGET_CONTEXT
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: RelocInfo::CODE_TARGET);
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} else {
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// Inline the inobject property case.
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// Inline the in-object property case.
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Comment cmnt(masm(), "[ Inlined named property load");
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DeferredReferenceGetNamedValue* deferred =
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@ -5304,7 +5335,7 @@ void CodeGenerator::EmitNamedLoad(Handle<String> name, bool is_contextual) {
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__ cmp(r2, r3);
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deferred->Branch(ne);
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// Use initially use an invalid index. The index will be patched by the
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// Initially use an invalid index. The index will be patched by the
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// inline cache code.
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__ ldr(r0, MemOperand(r1, 0));
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@ -5318,13 +5349,81 @@ void CodeGenerator::EmitNamedLoad(Handle<String> name, bool is_contextual) {
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}
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void CodeGenerator::EmitKeyedLoad(bool is_global) {
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Comment cmnt(masm_, "[ Load from keyed Property");
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Handle<Code> ic(Builtins::builtin(Builtins::KeyedLoadIC_Initialize));
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RelocInfo::Mode rmode = is_global
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? RelocInfo::CODE_TARGET_CONTEXT
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: RelocInfo::CODE_TARGET;
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frame_->CallCodeObject(ic, rmode, 0);
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void CodeGenerator::EmitKeyedLoad() {
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if (loop_nesting() == 0) {
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Comment cmnt(masm_, "[ Load from keyed property");
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frame_->CallKeyedLoadIC();
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} else {
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// Inline the keyed load.
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Comment cmnt(masm_, "[ Inlined load from keyed property");
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DeferredReferenceGetKeyedValue* deferred =
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new DeferredReferenceGetKeyedValue();
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// Counter will be decremented in the deferred code. Placed here to avoid
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// having it in the instruction stream below where patching will occur.
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__ IncrementCounter(&Counters::keyed_load_inline, 1,
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frame_->scratch0(), frame_->scratch1());
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// Load the receiver from the stack.
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__ ldr(r0, MemOperand(sp, kPointerSize));
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// Check that the receiver is a heap object.
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__ tst(r0, Operand(kSmiTagMask));
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deferred->Branch(eq);
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// The following instructions are the inlined load keyed property. Parts
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// of this code are patched, so the exact number of instructions generated
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// need to be fixed. Therefore the constant pool is blocked while generating
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// this code.
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#ifdef DEBUG
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int kInlinedKeyedLoadInstructions = 20;
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Label check_inlined_codesize;
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masm_->bind(&check_inlined_codesize);
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#endif
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{ Assembler::BlockConstPoolScope block_const_pool(masm_);
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// Check the map. The null map used below is patched by the inline cache
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// code.
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__ ldr(r1, FieldMemOperand(r0, HeapObject::kMapOffset));
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__ mov(r2, Operand(Factory::null_value()));
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__ cmp(r1, r2);
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deferred->Branch(ne);
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// Load the key from the stack.
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__ ldr(r1, MemOperand(sp, 0));
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// Check that the key is a smi.
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__ tst(r1, Operand(kSmiTagMask));
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deferred->Branch(ne);
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// Get the elements array from the receiver and check that it
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// is not a dictionary.
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__ ldr(r2, FieldMemOperand(r0, JSObject::kElementsOffset));
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__ ldr(r3, FieldMemOperand(r2, JSObject::kMapOffset));
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__ LoadRoot(r4, Heap::kFixedArrayMapRootIndex);
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__ cmp(r3, r4);
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deferred->Branch(ne);
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// Check that key is within bounds.
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__ ldr(r3, FieldMemOperand(r2, FixedArray::kLengthOffset));
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__ cmp(r3, Operand(r1, ASR, kSmiTagSize));
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deferred->Branch(ls); // Unsigned less equal.
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// Load and check that the result is not the hole (r1 is a smi).
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__ LoadRoot(r3, Heap::kTheHoleValueRootIndex);
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__ add(r2, r2, Operand(FixedArray::kHeaderSize - kHeapObjectTag));
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__ ldr(r0, MemOperand(r2, r1, LSL,
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kPointerSizeLog2 - (kSmiTagSize + kSmiShiftSize)));
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__ cmp(r0, r3);
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deferred->Branch(eq);
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// Make sure that the expected number of instructions are generated.
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ASSERT_EQ(kInlinedKeyedLoadInstructions,
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masm_->InstructionsGeneratedSince(&check_inlined_codesize));
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}
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deferred->BindExit();
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}
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}
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@ -5383,12 +5482,8 @@ void Reference::GetValue() {
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}
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case KEYED: {
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// TODO(181): Implement inlined version of array indexing once
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// loop nesting is properly tracked on ARM.
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ASSERT(property != NULL);
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Variable* var = expression_->AsVariableProxy()->AsVariable();
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ASSERT(var == NULL || var->is_global());
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cgen_->EmitKeyedLoad(var != NULL);
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cgen_->EmitKeyedLoad();
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cgen_->frame()->EmitPush(r0);
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break;
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}
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@ -157,7 +157,7 @@ enum ArgumentsAllocationMode {
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// states of the generated code.
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enum NopMarkerTypes {
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NON_MARKING_NOP = 0,
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NAMED_PROPERTY_LOAD_INLINED
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PROPERTY_LOAD_INLINED
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};
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@ -318,7 +318,7 @@ class CodeGenerator: public AstVisitor {
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// Load a keyed property, leaving it in r0. The receiver and key are
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// passed on the stack, and remain there.
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void EmitKeyedLoad(bool is_global);
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void EmitKeyedLoad();
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void LoadFromGlobalSlotCheckExtensions(Slot* slot,
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TypeofState typeof_state,
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@ -563,15 +563,8 @@ void LoadIC::GenerateMiss(MacroAssembler* masm) {
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}
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void LoadIC::ClearInlinedVersion(Address address) {
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// Reset the map check of the inlined inobject property load (if present) to
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// guarantee failure by holding an invalid map (the null value). The offset
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// can be patched to anything.
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PatchInlinedLoad(address, Heap::null_value(), 0);
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}
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bool LoadIC::PatchInlinedLoad(Address address, Object* map, int offset) {
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static inline bool IsInlinedICSite(Address address,
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Address* inline_end_address) {
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// If the instruction after the call site is not the pseudo instruction nop1
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// then this is not related to an inlined in-object property load. The nop1
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// instruction is located just after the call to the IC in the deferred code
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@ -579,24 +572,42 @@ bool LoadIC::PatchInlinedLoad(Address address, Object* map, int offset) {
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// a branch instruction for jumping back from the deferred code.
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Address address_after_call = address + Assembler::kCallTargetAddressOffset;
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Instr instr_after_call = Assembler::instr_at(address_after_call);
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if (!Assembler::IsNop(instr_after_call, NAMED_PROPERTY_LOAD_INLINED)) {
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if (!Assembler::IsNop(instr_after_call, PROPERTY_LOAD_INLINED)) {
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return false;
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}
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ASSERT_EQ(0, RegisterAllocator::kNumRegisters);
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Address address_after_nop1 = address_after_call + Assembler::kInstrSize;
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Instr instr_after_nop1 = Assembler::instr_at(address_after_nop1);
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ASSERT(Assembler::IsBranch(instr_after_nop1));
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Address address_after_nop = address_after_call + Assembler::kInstrSize;
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Instr instr_after_nop = Assembler::instr_at(address_after_nop);
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ASSERT(Assembler::IsBranch(instr_after_nop));
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// Find the end of the inlined code for handling the load.
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int b_offset =
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Assembler::GetBranchOffset(instr_after_nop1) + Assembler::kPcLoadDelta;
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Assembler::GetBranchOffset(instr_after_nop) + Assembler::kPcLoadDelta;
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ASSERT(b_offset < 0); // Jumping back from deferred code.
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Address inline_end_address = address_after_nop1 + b_offset;
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*inline_end_address = address_after_nop + b_offset;
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return true;
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}
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void LoadIC::ClearInlinedVersion(Address address) {
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// Reset the map check of the inlined in-object property load (if present) to
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// guarantee failure by holding an invalid map (the null value). The offset
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// can be patched to anything.
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PatchInlinedLoad(address, Heap::null_value(), 0);
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}
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bool LoadIC::PatchInlinedLoad(Address address, Object* map, int offset) {
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// Find the end of the inlined code for handling the load if this is an
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// inlined IC call site.
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Address inline_end_address;
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if (!IsInlinedICSite(address, &inline_end_address)) return false;
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// Patch the offset of the property load instruction (ldr r0, [r1, #+XXX]).
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// The immediate must be represenatble in 12 bits.
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// The immediate must be representable in 12 bits.
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ASSERT((JSObject::kMaxInstanceSize - JSObject::kHeaderSize) < (1 << 12));
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Address ldr_property_instr_address = inline_end_address - 4;
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Address ldr_property_instr_address =
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inline_end_address - Assembler::kInstrSize;
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ASSERT(Assembler::IsLdrRegisterImmediate(
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Assembler::instr_at(ldr_property_instr_address)));
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Instr ldr_property_instr = Assembler::instr_at(ldr_property_instr_address);
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@ -608,18 +619,31 @@ bool LoadIC::PatchInlinedLoad(Address address, Object* map, int offset) {
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CPU::FlushICache(ldr_property_instr_address, 1 * Assembler::kInstrSize);
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// Patch the map check.
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Address ldr_map_instr_address = inline_end_address - 16;
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Address ldr_map_instr_address =
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inline_end_address - 4 * Assembler::kInstrSize;
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Assembler::set_target_address_at(ldr_map_instr_address,
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reinterpret_cast<Address>(map));
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return true;
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}
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void KeyedLoadIC::ClearInlinedVersion(Address address) {}
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void KeyedLoadIC::ClearInlinedVersion(Address address) {
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// Reset the map check of the inlined keyed load (if present) to
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// guarantee failure by holding an invalid map (the null value).
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PatchInlinedLoad(address, Heap::null_value());
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}
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bool KeyedLoadIC::PatchInlinedLoad(Address address, Object* map) {
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return false;
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Address inline_end_address;
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if (!IsInlinedICSite(address, &inline_end_address)) return false;
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// Patch the map check.
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Address ldr_map_instr_address =
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inline_end_address - 19 * Assembler::kInstrSize;
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Assembler::set_target_address_at(ldr_map_instr_address,
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reinterpret_cast<Address>(map));
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return true;
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}
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@ -303,6 +303,12 @@ void VirtualFrame::CallLoadIC(RelocInfo::Mode mode) {
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}
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void VirtualFrame::CallKeyedLoadIC() {
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Handle<Code> ic(Builtins::builtin(Builtins::KeyedLoadIC_Initialize));
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CallCodeObject(ic, RelocInfo::CODE_TARGET, 0);
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}
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void VirtualFrame::CallCodeObject(Handle<Code> code,
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RelocInfo::Mode rmode,
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int dropped_args) {
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@ -308,10 +308,14 @@ class VirtualFrame : public ZoneObject {
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InvokeJSFlags flag,
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int arg_count);
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// Call load IC. Receiver on stack and property name in r2. Result returned in
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// r0.
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// Call load IC. Receiver is on the stack and the property name is in r2.
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// Result is returned in r0.
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void CallLoadIC(RelocInfo::Mode mode);
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// Call keyed load IC. Key and receiver are on the stack. Result is returned
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// in r0.
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void CallKeyedLoadIC();
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// Call into an IC stub given the number of arguments it removes
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// from the stack. Register arguments to the IC stub are implicit,
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// and depend on the type of IC stub.
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