AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

Simplify AssemblerPositionsRecorder.

Browse Source 
R=bmeurer@chromium.org, jgruber@chromium.org

Review-Url: https://codereview.chromium.org/2072963003
Cr-Commit-Position: refs/heads/master@{#37089}
This commit is contained in:
yangguo 2016-06-20 00:29:58 -07:00 committed by Commit bot
parent 3c9ff7ecf8
commit 9c3d730d42
30 changed files with 29 additions and 172 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/arm/assembler-arm.cc
View File

@ -1378,7 +1378,6 @@ void Assembler::b(int branch_offset, Condition cond) {
void Assembler::bl(int branch_offset, Condition cond) {
positions_recorder()->WriteRecordedPositions();
DCHECK((branch_offset & 3) == 0);
int imm24 = branch_offset >> 2;
CHECK(is_int24(imm24));
@ -1387,7 +1386,6 @@ void Assembler::bl(int branch_offset, Condition cond) {
void Assembler::blx(int branch_offset) { // v5 and above
positions_recorder()->WriteRecordedPositions();
DCHECK((branch_offset & 1) == 0);
int h = ((branch_offset & 2) >> 1)*B24;
int imm24 = branch_offset >> 2;
@ -1397,14 +1395,12 @@ void Assembler::blx(int branch_offset) { // v5 and above
void Assembler::blx(Register target, Condition cond) { // v5 and above
positions_recorder()->WriteRecordedPositions();
DCHECK(!target.is(pc));
emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BLX | target.code());
}
void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t
positions_recorder()->WriteRecordedPositions();
DCHECK(!target.is(pc)); // use of pc is actually allowed, but discouraged
emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | BX | target.code());
}
@ -1512,9 +1508,6 @@ void Assembler::orr(Register dst, Register src1, const Operand& src2,
void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
if (dst.is(pc)) {
positions_recorder()->WriteRecordedPositions();
}
// Don't allow nop instructions in the form mov rn, rn to be generated using
// the mov instruction. They must be generated using nop(int/NopMarkerTypes)
// or MarkCode(int/NopMarkerTypes) pseudo instructions.
@ -2003,9 +1996,6 @@ void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
// Load/Store instructions.
void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
if (dst.is(pc)) {
positions_recorder()->WriteRecordedPositions();
}
addrmod2(cond | B26 | L, dst, src);
}

6
src/arm/macro-assembler-arm.cc
View File

@ -120,12 +120,6 @@ void MacroAssembler::Call(Address target,
// blx ip
// @ return address
// Statement positions are expected to be recorded when the target
// address is loaded. The mov method will automatically record
// positions when pc is the target, since this is not the case here
// we have to do it explicitly.
positions_recorder()->WriteRecordedPositions();
mov(ip, Operand(reinterpret_cast<int32_t>(target), rmode));
blx(ip, cond);

15
src/arm64/assembler-arm64.cc
View File

@ -971,14 +971,12 @@ void Assembler::EndBlockVeneerPool() {
void Assembler::br(const Register& xn) {
positions_recorder()->WriteRecordedPositions();
DCHECK(xn.Is64Bits());
Emit(BR | Rn(xn));
}
void Assembler::blr(const Register& xn) {
positions_recorder()->WriteRecordedPositions();
DCHECK(xn.Is64Bits());
// The pattern 'blr xzr' is used as a guard to detect when execution falls
// through the constant pool. It should not be emitted.
@ -988,7 +986,6 @@ void Assembler::blr(const Register& xn) {
void Assembler::ret(const Register& xn) {
positions_recorder()->WriteRecordedPositions();
DCHECK(xn.Is64Bits());
Emit(RET | Rn(xn));
}
@ -1000,7 +997,6 @@ void Assembler::b(int imm26) {
void Assembler::b(Label* label) {
positions_recorder()->WriteRecordedPositions();
b(LinkAndGetInstructionOffsetTo(label));
}
@ -1011,47 +1007,40 @@ void Assembler::b(int imm19, Condition cond) {
void Assembler::b(Label* label, Condition cond) {
positions_recorder()->WriteRecordedPositions();
b(LinkAndGetInstructionOffsetTo(label), cond);
}
void Assembler::bl(int imm26) {
positions_recorder()->WriteRecordedPositions();
Emit(BL | ImmUncondBranch(imm26));
}
void Assembler::bl(Label* label) {
positions_recorder()->WriteRecordedPositions();
bl(LinkAndGetInstructionOffsetTo(label));
}
void Assembler::cbz(const Register& rt,
int imm19) {
positions_recorder()->WriteRecordedPositions();
Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
}
void Assembler::cbz(const Register& rt,
Label* label) {
positions_recorder()->WriteRecordedPositions();
cbz(rt, LinkAndGetInstructionOffsetTo(label));
}
void Assembler::cbnz(const Register& rt,
int imm19) {
positions_recorder()->WriteRecordedPositions();
Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
}
void Assembler::cbnz(const Register& rt,
Label* label) {
positions_recorder()->WriteRecordedPositions();
cbnz(rt, LinkAndGetInstructionOffsetTo(label));
}
@ -1059,7 +1048,6 @@ void Assembler::cbnz(const Register& rt,
void Assembler::tbz(const Register& rt,
unsigned bit_pos,
int imm14) {
positions_recorder()->WriteRecordedPositions();
DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
}
@ -1068,7 +1056,6 @@ void Assembler::tbz(const Register& rt,
void Assembler::tbz(const Register& rt,
unsigned bit_pos,
Label* label) {
positions_recorder()->WriteRecordedPositions();
tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
}
@ -1076,7 +1063,6 @@ void Assembler::tbz(const Register& rt,
void Assembler::tbnz(const Register& rt,
unsigned bit_pos,
int imm14) {
positions_recorder()->WriteRecordedPositions();
DCHECK(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
}
@ -1085,7 +1071,6 @@ void Assembler::tbnz(const Register& rt,
void Assembler::tbnz(const Register& rt,
unsigned bit_pos,
Label* label) {
positions_recorder()->WriteRecordedPositions();
tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
}

3
src/arm64/macro-assembler-arm64.cc
View File

@ -1971,9 +1971,6 @@ void MacroAssembler::Call(Address target, RelocInfo::Mode rmode) {
Label start_call;
Bind(&start_call);
#endif
// Statement positions are expected to be recorded when the target
// address is loaded.
positions_recorder()->WriteRecordedPositions();
// Addresses always have 64 bits, so we shouldn't encounter NONE32.
DCHECK(rmode != RelocInfo::NONE32);

24
src/assembler.cc
View File

@ -1826,25 +1826,27 @@ std::ostream& operator<<(std::ostream& os, ExternalReference reference) {
return os;
}
void AssemblerPositionsRecorder::RecordPosition(int pos) {
bool AssemblerPositionsRecorder::RecordPosition(int pos) {
DCHECK(pos != RelocInfo::kNoPosition);
DCHECK(pos >= 0);
state_.current_position = pos;
current_position_ = pos;
LOG_CODE_EVENT(assembler_->isolate(),
CodeLinePosInfoAddPositionEvent(jit_handler_data_,
assembler_->pc_offset(),
pos));
return WriteRecordedPositions();
}
void AssemblerPositionsRecorder::RecordStatementPosition(int pos) {
bool AssemblerPositionsRecorder::RecordStatementPosition(int pos) {
DCHECK(pos != RelocInfo::kNoPosition);
DCHECK(pos >= 0);
state_.current_statement_position = pos;
current_statement_position_ = pos;
LOG_CODE_EVENT(assembler_->isolate(),
CodeLinePosInfoAddStatementPositionEvent(
jit_handler_data_,
assembler_->pc_offset(),
pos));
return RecordPosition(pos);
}
bool AssemblerPositionsRecorder::WriteRecordedPositions() {
@ -1852,21 +1854,21 @@ bool AssemblerPositionsRecorder::WriteRecordedPositions() {
// Write the statement position if it is different from what was written last
// time.
if (state_.current_statement_position != state_.written_statement_position) {
if (current_statement_position_ != written_statement_position_) {
EnsureSpace ensure_space(assembler_);
assembler_->RecordRelocInfo(RelocInfo::STATEMENT_POSITION,
state_.current_statement_position);
state_.written_position = state_.current_statement_position;
state_.written_statement_position = state_.current_statement_position;
current_statement_position_);
written_position_ = current_statement_position_;
written_statement_position_ = current_statement_position_;
written = true;
}
// Write the position if it is different from what was written last time and
// also different from the statement position that was just written.
if (state_.current_position != state_.written_position) {
if (current_position_ != written_position_) {
EnsureSpace ensure_space(assembler_);
assembler_->RecordRelocInfo(RelocInfo::POSITION, state_.current_position);
state_.written_position = state_.current_position;
assembler_->RecordRelocInfo(RelocInfo::POSITION, current_position_);
written_position_ = current_position_;
written = true;
}

38
src/assembler.h
View File

@ -1142,42 +1142,32 @@ std::ostream& operator<<(std::ostream&, ExternalReference);
// -----------------------------------------------------------------------------
// Position recording support
struct PositionState {
PositionState() : current_position(RelocInfo::kNoPosition),
written_position(RelocInfo::kNoPosition),
current_statement_position(RelocInfo::kNoPosition),
written_statement_position(RelocInfo::kNoPosition) {}
int current_position;
int written_position;
int current_statement_position;
int written_statement_position;
};
class AssemblerPositionsRecorder : public PositionsRecorder {
public:
explicit AssemblerPositionsRecorder(Assembler* assembler)
: assembler_(assembler) {}
: assembler_(assembler),
current_position_(RelocInfo::kNoPosition),
written_position_(RelocInfo::kNoPosition),
current_statement_position_(RelocInfo::kNoPosition),
written_statement_position_(RelocInfo::kNoPosition) {}
// Set current position to pos.
void RecordPosition(int pos);
bool RecordPosition(int pos);
// Set current statement position to pos.
void RecordStatementPosition(int pos);
bool RecordStatementPosition(int pos);
private:
// Write recorded positions to relocation information.
bool WriteRecordedPositions();
int current_position() const { return state_.current_position; }
int current_statement_position() const {
return state_.current_statement_position;
}
private:
Assembler* assembler_;
PositionState state_;
int current_position_;
int written_position_;
int current_statement_position_;
int written_statement_position_;
DISALLOW_COPY_AND_ASSIGN(AssemblerPositionsRecorder);
};

1
src/compiler/code-generator.cc
View File

@ -399,7 +399,6 @@ void CodeGenerator::AssembleSourcePosition(Instruction* instr) {
if (source_position.IsUnknown()) return;
int code_pos = source_position.raw();
masm()->positions_recorder()->RecordPosition(code_pos);
masm()->positions_recorder()->WriteRecordedPositions();
if (FLAG_code_comments) {
CompilationInfo* info = this->info();
if (!info->parse_info()) return;

1
src/crankshaft/arm/lithium-codegen-arm.cc
View File

@ -909,7 +909,6 @@ void LCodeGen::RecordSafepointWithRegisters(LPointerMap* pointers,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}

1
src/crankshaft/arm64/lithium-codegen-arm64.cc
View File

@ -448,7 +448,6 @@ void LCodeGen::CallRuntimeFromDeferred(Runtime::FunctionId id,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}

1
src/crankshaft/ia32/lithium-codegen-ia32.cc
View File

@ -810,7 +810,6 @@ void LCodeGen::RecordSafepointWithRegisters(LPointerMap* pointers,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}

1
src/crankshaft/mips/lithium-codegen-mips.cc
View File

@ -875,7 +875,6 @@ void LCodeGen::RecordSafepointWithRegisters(LPointerMap* pointers,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}

1
src/crankshaft/mips64/lithium-codegen-mips64.cc
View File

@ -864,7 +864,6 @@ void LCodeGen::RecordSafepointWithRegisters(LPointerMap* pointers,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}

1
src/crankshaft/ppc/lithium-codegen-ppc.cc
View File

@ -836,7 +836,6 @@ void LCodeGen::RecordSafepointWithRegisters(LPointerMap* pointers,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}

1
src/crankshaft/s390/lithium-codegen-s390.cc
View File

@ -819,7 +819,6 @@ void LCodeGen::RecordSafepointWithRegisters(LPointerMap* pointers,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}
static const char* LabelType(LLabel* label) {

1
src/crankshaft/x64/lithium-codegen-x64.cc
View File

@ -838,7 +838,6 @@ void LCodeGen::RecordSafepointWithRegisters(LPointerMap* pointers,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}

1
src/crankshaft/x87/lithium-codegen-x87.cc
View File

@ -1101,7 +1101,6 @@ void LCodeGen::RecordSafepointWithRegisters(LPointerMap* pointers,
void LCodeGen::RecordAndWritePosition(int position) {
if (position == RelocInfo::kNoPosition) return;
masm()->positions_recorder()->RecordPosition(position);
masm()->positions_recorder()->WriteRecordedPositions();
}

7
src/full-codegen/full-codegen.cc
View File

@ -617,16 +617,13 @@ void FullCodeGenerator::EmitHasProperty() {
bool RecordStatementPosition(MacroAssembler* masm, int pos) {
if (pos == RelocInfo::kNoPosition) return false;
masm->positions_recorder()->RecordStatementPosition(pos);
masm->positions_recorder()->RecordPosition(pos);
return masm->positions_recorder()->WriteRecordedPositions();
return masm->positions_recorder()->RecordStatementPosition(pos);
}
bool RecordPosition(MacroAssembler* masm, int pos) {
if (pos == RelocInfo::kNoPosition) return false;
masm->positions_recorder()->RecordPosition(pos);
return masm->positions_recorder()->WriteRecordedPositions();
return masm->positions_recorder()->RecordPosition(pos);
}

4
src/ia32/assembler-ia32.cc
View File

@ -1531,7 +1531,6 @@ void Assembler::bind(Label* L) {
void Assembler::call(Label* L) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
if (L->is_bound()) {
const int long_size = 5;
@ -1549,7 +1548,6 @@ void Assembler::call(Label* L) {
void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
DCHECK(!RelocInfo::IsCodeTarget(rmode));
EMIT(0xE8);
@ -1568,7 +1566,6 @@ int Assembler::CallSize(const Operand& adr) {
void Assembler::call(const Operand& adr) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
EMIT(0xFF);
emit_operand(edx, adr);
@ -1583,7 +1580,6 @@ int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
void Assembler::call(Handle<Code> code,
RelocInfo::Mode rmode,
TypeFeedbackId ast_id) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
DCHECK(RelocInfo::IsCodeTarget(rmode)
|| rmode == RelocInfo::CODE_AGE_SEQUENCE);

17
src/mips/assembler-mips.cc
View File

@ -1266,7 +1266,6 @@ void Assembler::b(int16_t offset) {
void Assembler::bal(int16_t offset) {
positions_recorder()->WriteRecordedPositions();
bgezal(zero_reg, offset);
}
@ -1279,7 +1278,6 @@ void Assembler::bc(int32_t offset) {
void Assembler::balc(int32_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BALC, offset, CompactBranchType::COMPACT_BRANCH);
}
@ -1326,7 +1324,6 @@ void Assembler::bgec(Register rs, Register rt, int16_t offset) {
void Assembler::bgezal(Register rs, int16_t offset) {
DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg));
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1397,7 +1394,6 @@ void Assembler::bltz(Register rs, int16_t offset) {
void Assembler::bltzal(Register rs, int16_t offset) {
DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg));
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1433,7 +1429,6 @@ void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
void Assembler::blezalc(Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BLEZ, zero_reg, rt, offset,
CompactBranchType::COMPACT_BRANCH);
}
@ -1442,7 +1437,6 @@ void Assembler::blezalc(Register rt, int16_t offset) {
void Assembler::bgezalc(Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BLEZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
}
@ -1451,7 +1445,6 @@ void Assembler::bgezall(Register rs, int16_t offset) {
DCHECK(!IsMipsArchVariant(kMips32r6));
DCHECK(!(rs.is(zero_reg)));
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(REGIMM, rs, BGEZALL, offset);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1460,7 +1453,6 @@ void Assembler::bgezall(Register rs, int16_t offset) {
void Assembler::bltzalc(Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BGTZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
}
@ -1468,7 +1460,6 @@ void Assembler::bltzalc(Register rt, int16_t offset) {
void Assembler::bgtzalc(Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BGTZ, zero_reg, rt, offset,
CompactBranchType::COMPACT_BRANCH);
}
@ -1477,7 +1468,6 @@ void Assembler::bgtzalc(Register rt, int16_t offset) {
void Assembler::beqzalc(Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(ADDI, zero_reg, rt, offset,
CompactBranchType::COMPACT_BRANCH);
}
@ -1486,7 +1476,6 @@ void Assembler::beqzalc(Register rt, int16_t offset) {
void Assembler::bnezalc(Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(DADDI, zero_reg, rt, offset,
CompactBranchType::COMPACT_BRANCH);
}
@ -1545,9 +1534,6 @@ void Assembler::j(int32_t target) {
void Assembler::jr(Register rs) {
if (!IsMipsArchVariant(kMips32r6)) {
BlockTrampolinePoolScope block_trampoline_pool(this);
if (rs.is(ra)) {
positions_recorder()->WriteRecordedPositions();
}
GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
BlockTrampolinePoolFor(1); // For associated delay slot.
} else {
@ -1565,7 +1551,6 @@ void Assembler::jal(int32_t target) {
DCHECK(in_range && ((target & 3) == 0));
#endif
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrJump(JAL, (target >> 2) & kImm26Mask);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1574,7 +1559,6 @@ void Assembler::jal(int32_t target) {
void Assembler::jalr(Register rs, Register rd) {
DCHECK(rs.code() != rd.code());
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1588,7 +1572,6 @@ void Assembler::jic(Register rt, int16_t offset) {
void Assembler::jialc(Register rt, int16_t offset) {
DCHECK(IsMipsArchVariant(kMips32r6));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(POP76, zero_reg, rt, offset);
}

3
src/mips/macro-assembler-mips.cc
View File

@ -3832,9 +3832,6 @@ void MacroAssembler::Call(Address target,
Label start;
bind(&start);
int32_t target_int = reinterpret_cast<int32_t>(target);
// Must record previous source positions before the
// li() generates a new code target.
positions_recorder()->WriteRecordedPositions();
li(t9, Operand(target_int, rmode), CONSTANT_SIZE);
Call(t9, cond, rs, rt, bd);
DCHECK_EQ(CallSize(target, rmode, cond, rs, rt, bd),

18
src/mips64/assembler-mips64.cc
View File

@ -1252,7 +1252,6 @@ void Assembler::b(int16_t offset) {
void Assembler::bal(int16_t offset) {
positions_recorder()->WriteRecordedPositions();
bgezal(zero_reg, offset);
}
@ -1265,7 +1264,6 @@ void Assembler::bc(int32_t offset) {
void Assembler::balc(int32_t offset) {
DCHECK(kArchVariant == kMips64r6);
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BALC, offset, CompactBranchType::COMPACT_BRANCH);
}
@ -1312,7 +1310,6 @@ void Assembler::bgec(Register rs, Register rt, int16_t offset) {
void Assembler::bgezal(Register rs, int16_t offset) {
DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg));
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1383,7 +1380,6 @@ void Assembler::bltz(Register rs, int16_t offset) {
void Assembler::bltzal(Register rs, int16_t offset) {
DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg));
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1419,7 +1415,6 @@ void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
void Assembler::blezalc(Register rt, int16_t offset) {
DCHECK(kArchVariant == kMips64r6);
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BLEZ, zero_reg, rt, offset,
CompactBranchType::COMPACT_BRANCH);
}
@ -1428,7 +1423,6 @@ void Assembler::blezalc(Register rt, int16_t offset) {
void Assembler::bgezalc(Register rt, int16_t offset) {
DCHECK(kArchVariant == kMips64r6);
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BLEZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
}
@ -1437,7 +1431,6 @@ void Assembler::bgezall(Register rs, int16_t offset) {
DCHECK(kArchVariant != kMips64r6);
DCHECK(!(rs.is(zero_reg)));
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(REGIMM, rs, BGEZALL, offset);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1446,7 +1439,6 @@ void Assembler::bgezall(Register rs, int16_t offset) {
void Assembler::bltzalc(Register rt, int16_t offset) {
DCHECK(kArchVariant == kMips64r6);
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BGTZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
}
@ -1454,7 +1446,6 @@ void Assembler::bltzalc(Register rt, int16_t offset) {
void Assembler::bgtzalc(Register rt, int16_t offset) {
DCHECK(kArchVariant == kMips64r6);
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(BGTZ, zero_reg, rt, offset,
CompactBranchType::COMPACT_BRANCH);
}
@ -1463,7 +1454,6 @@ void Assembler::bgtzalc(Register rt, int16_t offset) {
void Assembler::beqzalc(Register rt, int16_t offset) {
DCHECK(kArchVariant == kMips64r6);
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(ADDI, zero_reg, rt, offset,
CompactBranchType::COMPACT_BRANCH);
}
@ -1472,7 +1462,6 @@ void Assembler::beqzalc(Register rt, int16_t offset) {
void Assembler::bnezalc(Register rt, int16_t offset) {
DCHECK(kArchVariant == kMips64r6);
DCHECK(!(rt.is(zero_reg)));
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(DADDI, zero_reg, rt, offset,
CompactBranchType::COMPACT_BRANCH);
}
@ -1538,7 +1527,6 @@ void Assembler::jal(Label* target) {
uint64_t imm = jump_offset(target);
if (target->is_bound()) {
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrJump(static_cast<Opcode>(kJalRawMark),
static_cast<uint32_t>(imm >> 2) & kImm26Mask);
BlockTrampolinePoolFor(1); // For associated delay slot.
@ -1551,9 +1539,6 @@ void Assembler::jal(Label* target) {
void Assembler::jr(Register rs) {
if (kArchVariant != kMips64r6) {
BlockTrampolinePoolScope block_trampoline_pool(this);
if (rs.is(ra)) {
positions_recorder()->WriteRecordedPositions();
}
GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
BlockTrampolinePoolFor(1); // For associated delay slot.
} else {
@ -1564,7 +1549,6 @@ void Assembler::jr(Register rs) {
void Assembler::jal(int64_t target) {
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrJump(JAL, static_cast<uint32_t>(target >> 2) & kImm26Mask);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1573,7 +1557,6 @@ void Assembler::jal(int64_t target) {
void Assembler::jalr(Register rs, Register rd) {
DCHECK(rs.code() != rd.code());
BlockTrampolinePoolScope block_trampoline_pool(this);
positions_recorder()->WriteRecordedPositions();
GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
BlockTrampolinePoolFor(1); // For associated delay slot.
}
@ -1587,7 +1570,6 @@ void Assembler::jic(Register rt, int16_t offset) {
void Assembler::jialc(Register rt, int16_t offset) {
DCHECK(kArchVariant == kMips64r6);
positions_recorder()->WriteRecordedPositions();
GenInstrImmediate(POP76, zero_reg, rt, offset);
}

3
src/mips64/macro-assembler-mips64.cc
View File

@ -4031,9 +4031,6 @@ void MacroAssembler::Call(Address target,
Label start;
bind(&start);
int64_t target_int = reinterpret_cast<int64_t>(target);
// Must record previous source positions before the
// li() generates a new code target.
positions_recorder()->WriteRecordedPositions();
li(t9, Operand(target_int, rmode), ADDRESS_LOAD);
Call(t9, cond, rs, rt, bd);
DCHECK_EQ(CallSize(target, rmode, cond, rs, rt, bd),

8
src/ppc/assembler-ppc.cc
View File

@ -732,13 +732,11 @@ int Assembler::link(Label* L) {
void Assembler::bclr(BOfield bo, int condition_bit, LKBit lk) {
positions_recorder()->WriteRecordedPositions();
emit(EXT1 | bo | condition_bit * B16 | BCLRX | lk);
}
void Assembler::bcctr(BOfield bo, int condition_bit, LKBit lk) {
positions_recorder()->WriteRecordedPositions();
emit(EXT1 | bo | condition_bit * B16 | BCCTRX | lk);
}
@ -755,9 +753,6 @@ void Assembler::bctrl() { bcctr(BA, 0, SetLK); }
void Assembler::bc(int branch_offset, BOfield bo, int condition_bit, LKBit lk) {
if (lk == SetLK) {
positions_recorder()->WriteRecordedPositions();
}
int imm16 = branch_offset;
CHECK(is_int16(imm16) && (imm16 & (kAAMask | kLKMask)) == 0);
emit(BCX | bo | condition_bit * B16 | (imm16 & kImm16Mask) | lk);
@ -765,9 +760,6 @@ void Assembler::bc(int branch_offset, BOfield bo, int condition_bit, LKBit lk) {
void Assembler::b(int branch_offset, LKBit lk) {
if (lk == SetLK) {
positions_recorder()->WriteRecordedPositions();
}
int imm26 = branch_offset;
CHECK(is_int26(imm26) && (imm26 & (kAAMask | kLKMask)) == 0);
emit(BX | (imm26 & kImm26Mask) | lk);

9
src/ppc/macro-assembler-ppc.cc
View File

@ -84,10 +84,6 @@ void MacroAssembler::Call(Register target) {
Label start;
bind(&start);
// Statement positions are expected to be recorded when the target
// address is loaded.
positions_recorder()->WriteRecordedPositions();
// branch via link register and set LK bit for return point
mtctr(target);
bctrl();
@ -128,11 +124,6 @@ void MacroAssembler::Call(Address target, RelocInfo::Mode rmode,
Label start;
bind(&start);
#endif
// Statement positions are expected to be recorded when the target
// address is loaded.
positions_recorder()->WriteRecordedPositions();
// This can likely be optimized to make use of bc() with 24bit relative
//
// RecordRelocInfo(x.rmode_, x.imm_);

1
src/s390/assembler-s390.cc
View File

@ -2520,7 +2520,6 @@ void Assembler::srdl(Register r1, const Operand& opnd) {
void Assembler::call(Handle<Code> target, RelocInfo::Mode rmode,
TypeFeedbackId ast_id) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
int32_t target_index = emit_code_target(target, rmode, ast_id);

1
src/s390/assembler-s390.h
View File

@ -548,7 +548,6 @@ class Assembler : public AssemblerBase {
// Helper for unconditional branch to Label with update to save register
void b(Register r, Label* l) {
positions_recorder()->WriteRecordedPositions();
int32_t halfwords = branch_offset(l) / 2;
brasl(r, Operand(halfwords));
}

5
src/s390/code-stubs-s390.cc
View File

@ -1035,7 +1035,6 @@ void CEntryStub::Generate(MacroAssembler* masm) {
// zLinux ABI requires caller's frame to have sufficient space for callee
// preserved regsiter save area.
// __ lay(sp, MemOperand(sp, -kCalleeRegisterSaveAreaSize));
__ positions_recorder()->WriteRecordedPositions();
__ b(target);
__ bind(&return_label);
// __ la(sp, MemOperand(sp, +kCalleeRegisterSaveAreaSize));
@ -3094,10 +3093,6 @@ void CompareICStub::GenerateMiss(MacroAssembler* masm) {
void DirectCEntryStub::Generate(MacroAssembler* masm) {
__ CleanseP(r14);
// Statement positions are expected to be recorded when the target
// address is loaded.
__ positions_recorder()->WriteRecordedPositions();
__ b(ip); // Callee will return to R14 directly
}

9
src/s390/macro-assembler-s390.cc
View File

@ -70,10 +70,6 @@ void MacroAssembler::Call(Register target) {
Label start;
bind(&start);
// Statement positions are expected to be recorded when the target
// address is loaded.
positions_recorder()->WriteRecordedPositions();
// Branch to target via indirect branch
basr(r14, target);
@ -122,10 +118,6 @@ void MacroAssembler::Call(Address target, RelocInfo::Mode rmode,
bind(&start);
#endif
// Statement positions are expected to be recorded when the target
// address is loaded.
positions_recorder()->WriteRecordedPositions();
mov(ip, Operand(reinterpret_cast<intptr_t>(target), rmode));
basr(r14, ip);
@ -4757,7 +4749,6 @@ void MacroAssembler::Branch(Condition c, const Operand& opnd) {
// Branch On Count. Decrement R1, and branch if R1 != 0.
void MacroAssembler::BranchOnCount(Register r1, Label* l) {
int32_t offset = branch_offset(l);
positions_recorder()->WriteRecordedPositions();
if (is_int16(offset)) {
#if V8_TARGET_ARCH_S390X
brctg(r1, Operand(offset));

6
src/x64/assembler-x64.cc
View File

@ -833,7 +833,6 @@ void Assembler::bsfq(Register dst, const Operand& src) {
void Assembler::call(Label* L) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
// 1110 1000 #32-bit disp.
emit(0xE8);
@ -855,7 +854,6 @@ void Assembler::call(Label* L) {
void Assembler::call(Address entry, RelocInfo::Mode rmode) {
DCHECK(RelocInfo::IsRuntimeEntry(rmode));
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
// 1110 1000 #32-bit disp.
emit(0xE8);
@ -866,7 +864,6 @@ void Assembler::call(Address entry, RelocInfo::Mode rmode) {
void Assembler::call(Handle<Code> target,
RelocInfo::Mode rmode,
TypeFeedbackId ast_id) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
// 1110 1000 #32-bit disp.
emit(0xE8);
@ -875,7 +872,6 @@ void Assembler::call(Handle<Code> target,
void Assembler::call(Register adr) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
// Opcode: FF /2 r64.
emit_optional_rex_32(adr);
@ -885,7 +881,6 @@ void Assembler::call(Register adr) {
void Assembler::call(const Operand& op) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
// Opcode: FF /2 m64.
emit_optional_rex_32(op);
@ -899,7 +894,6 @@ void Assembler::call(const Operand& op) {
// same Code object. Should not be used when generating new code (use labels),
// but only when patching existing code.
void Assembler::call(Address target) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
// 1110 1000 #32-bit disp.
emit(0xE8);

4
src/x87/assembler-x87.cc
View File

@ -1414,7 +1414,6 @@ void Assembler::bind(Label* L) {
void Assembler::call(Label* L) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
if (L->is_bound()) {
const int long_size = 5;
@ -1432,7 +1431,6 @@ void Assembler::call(Label* L) {
void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
DCHECK(!RelocInfo::IsCodeTarget(rmode));
EMIT(0xE8);
@ -1451,7 +1449,6 @@ int Assembler::CallSize(const Operand& adr) {
void Assembler::call(const Operand& adr) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
EMIT(0xFF);
emit_operand(edx, adr);
@ -1466,7 +1463,6 @@ int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
void Assembler::call(Handle<Code> code,
RelocInfo::Mode rmode,
TypeFeedbackId ast_id) {
positions_recorder()->WriteRecordedPositions();
EnsureSpace ensure_space(this);
DCHECK(RelocInfo::IsCodeTarget(rmode)
|| rmode == RelocInfo::CODE_AGE_SEQUENCE);