[liftoff] Remove lambdas for binops with immediate
This is the same cleanup as in the previous CL, but for {EmitBinOpImm}.
This requires a minor change in the name of the emit functions with
immediate, to make them distinguishable from the emit functions with two
registers. We just append an "i" to the functions with immediate.
R=zhin@chromium.org
Bug: v8:10364
Change-Id: Ie3732a956698368a5f1fbe67334a13014cd2f354
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2129631
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66941}
This commit is contained in:
Clemens Backes
Commit Bot
parent
4c414a2265
commit
a1bd722799
@ -791,27 +791,27 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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Register rhs) { \
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instruction(dst, lhs, rhs); \
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}
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#define I32_BINOP_I(name, instruction) \
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I32_BINOP(name, instruction) \
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void LiftoffAssembler::emit_##name(Register dst, Register lhs, \
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int32_t imm) { \
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instruction(dst, lhs, Operand(imm)); \
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#define I32_BINOP_I(name, instruction) \
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I32_BINOP(name, instruction) \
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void LiftoffAssembler::emit_##name##i(Register dst, Register lhs, \
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int32_t imm) { \
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instruction(dst, lhs, Operand(imm)); \
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}
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#define I32_SHIFTOP(name, instruction) \
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void LiftoffAssembler::emit_##name(Register dst, Register src, \
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Register amount) { \
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UseScratchRegisterScope temps(this); \
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Register scratch = temps.Acquire(); \
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and_(scratch, amount, Operand(0x1f)); \
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instruction(dst, src, Operand(scratch)); \
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} \
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void LiftoffAssembler::emit_##name(Register dst, Register src, \
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int32_t amount) { \
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if (V8_LIKELY((amount & 31) != 0)) { \
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instruction(dst, src, Operand(amount & 31)); \
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} else if (dst != src) { \
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mov(dst, src); \
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} \
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#define I32_SHIFTOP(name, instruction) \
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void LiftoffAssembler::emit_##name(Register dst, Register src, \
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Register amount) { \
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UseScratchRegisterScope temps(this); \
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Register scratch = temps.Acquire(); \
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and_(scratch, amount, Operand(0x1f)); \
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instruction(dst, src, Operand(scratch)); \
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} \
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void LiftoffAssembler::emit_##name##i(Register dst, Register src, \
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int32_t amount) { \
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if (V8_LIKELY((amount & 31) != 0)) { \
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instruction(dst, src, Operand(amount & 31)); \
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} else if (dst != src) { \
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mov(dst, src); \
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} \
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}
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#define FP32_UNOP(name, instruction) \
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void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister src) { \
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@ -997,8 +997,8 @@ void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
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liftoff::I64Binop<&Assembler::add, &Assembler::adc>(this, dst, lhs, rhs);
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}
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void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm) {
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void LiftoffAssembler::emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm) {
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liftoff::I64BinopI<&Assembler::add, &Assembler::adc>(this, dst, lhs, imm);
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}
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@ -1057,8 +1057,8 @@ void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
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liftoff::I64Shiftop<&TurboAssembler::LslPair, true>(this, dst, src, amount);
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}
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void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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void LiftoffAssembler::emit_i64_shli(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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UseScratchRegisterScope temps(this);
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// {src.low_gp()} will still be needed after writing {dst.high_gp()}.
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Register src_low =
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@ -1072,8 +1072,8 @@ void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
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liftoff::I64Shiftop<&TurboAssembler::AsrPair, false>(this, dst, src, amount);
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}
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void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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void LiftoffAssembler::emit_i64_sari(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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UseScratchRegisterScope temps(this);
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// {src.high_gp()} will still be needed after writing {dst.low_gp()}.
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Register src_high =
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@ -1087,8 +1087,8 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
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liftoff::I64Shiftop<&TurboAssembler::LsrPair, false>(this, dst, src, amount);
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}
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void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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void LiftoffAssembler::emit_i64_shri(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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UseScratchRegisterScope temps(this);
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// {src.high_gp()} will still be needed after writing {dst.low_gp()}.
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Register src_high =
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@ -532,22 +532,22 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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Register rhs) { \
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instruction(dst.W(), lhs.W(), rhs.W()); \
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}
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#define I32_BINOP_I(name, instruction) \
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I32_BINOP(name, instruction) \
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void LiftoffAssembler::emit_##name(Register dst, Register lhs, \
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int32_t imm) { \
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instruction(dst.W(), lhs.W(), Immediate(imm)); \
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#define I32_BINOP_I(name, instruction) \
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I32_BINOP(name, instruction) \
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void LiftoffAssembler::emit_##name##i(Register dst, Register lhs, \
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int32_t imm) { \
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instruction(dst.W(), lhs.W(), Immediate(imm)); \
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}
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#define I64_BINOP(name, instruction) \
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void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
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LiftoffRegister rhs) { \
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instruction(dst.gp().X(), lhs.gp().X(), rhs.gp().X()); \
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}
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#define I64_BINOP_I(name, instruction) \
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I64_BINOP(name, instruction) \
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void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
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int32_t imm) { \
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instruction(dst.gp().X(), lhs.gp().X(), imm); \
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#define I64_BINOP_I(name, instruction) \
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I64_BINOP(name, instruction) \
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void LiftoffAssembler::emit_##name##i(LiftoffRegister dst, \
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LiftoffRegister lhs, int32_t imm) { \
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instruction(dst.gp().X(), lhs.gp().X(), imm); \
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}
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#define FP32_BINOP(name, instruction) \
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void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister lhs, \
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@ -577,22 +577,22 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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instruction(dst.D(), src.D()); \
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return true; \
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}
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#define I32_SHIFTOP(name, instruction) \
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void LiftoffAssembler::emit_##name(Register dst, Register src, \
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Register amount) { \
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instruction(dst.W(), src.W(), amount.W()); \
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} \
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void LiftoffAssembler::emit_##name(Register dst, Register src, \
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int32_t amount) { \
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instruction(dst.W(), src.W(), amount & 31); \
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#define I32_SHIFTOP(name, instruction) \
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void LiftoffAssembler::emit_##name(Register dst, Register src, \
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Register amount) { \
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instruction(dst.W(), src.W(), amount.W()); \
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} \
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void LiftoffAssembler::emit_##name##i(Register dst, Register src, \
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int32_t amount) { \
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instruction(dst.W(), src.W(), amount & 31); \
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}
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#define I64_SHIFTOP(name, instruction) \
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void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister src, \
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Register amount) { \
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instruction(dst.gp().X(), src.gp().X(), amount.X()); \
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} \
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void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister src, \
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int32_t amount) { \
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void LiftoffAssembler::emit_##name##i(LiftoffRegister dst, \
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LiftoffRegister src, int32_t amount) { \
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instruction(dst.gp().X(), src.gp().X(), amount & 63); \
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}
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@ -686,7 +686,7 @@ void LiftoffAssembler::emit_i32_add(Register dst, Register lhs, Register rhs) {
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}
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}
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void LiftoffAssembler::emit_i32_add(Register dst, Register lhs, int32_t imm) {
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void LiftoffAssembler::emit_i32_addi(Register dst, Register lhs, int32_t imm) {
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if (lhs != dst) {
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lea(dst, Operand(lhs, imm));
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} else {
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@ -829,7 +829,7 @@ void LiftoffAssembler::emit_i32_and(Register dst, Register lhs, Register rhs) {
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liftoff::EmitCommutativeBinOp<&Assembler::and_>(this, dst, lhs, rhs);
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}
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void LiftoffAssembler::emit_i32_and(Register dst, Register lhs, int32_t imm) {
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void LiftoffAssembler::emit_i32_andi(Register dst, Register lhs, int32_t imm) {
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liftoff::EmitCommutativeBinOpImm<&Assembler::and_>(this, dst, lhs, imm);
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}
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@ -837,7 +837,7 @@ void LiftoffAssembler::emit_i32_or(Register dst, Register lhs, Register rhs) {
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liftoff::EmitCommutativeBinOp<&Assembler::or_>(this, dst, lhs, rhs);
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}
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void LiftoffAssembler::emit_i32_or(Register dst, Register lhs, int32_t imm) {
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void LiftoffAssembler::emit_i32_ori(Register dst, Register lhs, int32_t imm) {
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liftoff::EmitCommutativeBinOpImm<&Assembler::or_>(this, dst, lhs, imm);
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}
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@ -845,7 +845,7 @@ void LiftoffAssembler::emit_i32_xor(Register dst, Register lhs, Register rhs) {
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liftoff::EmitCommutativeBinOp<&Assembler::xor_>(this, dst, lhs, rhs);
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}
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void LiftoffAssembler::emit_i32_xor(Register dst, Register lhs, int32_t imm) {
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void LiftoffAssembler::emit_i32_xori(Register dst, Register lhs, int32_t imm) {
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liftoff::EmitCommutativeBinOpImm<&Assembler::xor_>(this, dst, lhs, imm);
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}
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@ -891,8 +891,8 @@ void LiftoffAssembler::emit_i32_shl(Register dst, Register src,
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liftoff::EmitShiftOperation(this, dst, src, amount, &Assembler::shl_cl);
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}
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void LiftoffAssembler::emit_i32_shl(Register dst, Register src,
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int32_t amount) {
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void LiftoffAssembler::emit_i32_shli(Register dst, Register src,
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int32_t amount) {
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if (dst != src) mov(dst, src);
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shl(dst, amount & 31);
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}
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@ -902,8 +902,8 @@ void LiftoffAssembler::emit_i32_sar(Register dst, Register src,
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liftoff::EmitShiftOperation(this, dst, src, amount, &Assembler::sar_cl);
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}
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void LiftoffAssembler::emit_i32_sar(Register dst, Register src,
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int32_t amount) {
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void LiftoffAssembler::emit_i32_sari(Register dst, Register src,
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int32_t amount) {
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if (dst != src) mov(dst, src);
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sar(dst, amount & 31);
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}
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@ -913,8 +913,8 @@ void LiftoffAssembler::emit_i32_shr(Register dst, Register src,
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liftoff::EmitShiftOperation(this, dst, src, amount, &Assembler::shr_cl);
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}
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void LiftoffAssembler::emit_i32_shr(Register dst, Register src,
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int32_t amount) {
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void LiftoffAssembler::emit_i32_shri(Register dst, Register src,
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int32_t amount) {
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if (dst != src) mov(dst, src);
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shr(dst, amount & 31);
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}
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@ -1001,8 +1001,8 @@ void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
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liftoff::OpWithCarry<&Assembler::add, &Assembler::adc>(this, dst, lhs, rhs);
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}
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void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm) {
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void LiftoffAssembler::emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm) {
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liftoff::OpWithCarryI<&Assembler::add, &Assembler::adc>(this, dst, lhs, imm);
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}
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@ -1137,8 +1137,8 @@ void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
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&TurboAssembler::ShlPair_cl);
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}
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void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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void LiftoffAssembler::emit_i64_shli(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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amount &= 63;
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if (amount >= 32) {
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if (dst.high_gp() != src.low_gp()) mov(dst.high_gp(), src.low_gp());
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@ -1156,8 +1156,8 @@ void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
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&TurboAssembler::SarPair_cl);
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}
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void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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void LiftoffAssembler::emit_i64_sari(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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amount &= 63;
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if (amount >= 32) {
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if (dst.low_gp() != src.high_gp()) mov(dst.low_gp(), src.high_gp());
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@ -1175,8 +1175,8 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
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&TurboAssembler::ShrPair_cl);
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}
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void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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void LiftoffAssembler::emit_i64_shri(LiftoffRegister dst, LiftoffRegister src,
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int32_t amount) {
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amount &= 63;
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if (amount >= 32) {
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if (dst.low_gp() != src.high_gp()) mov(dst.low_gp(), src.high_gp());
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@ -515,7 +515,7 @@ class LiftoffAssembler : public TurboAssembler {
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// i32 binops.
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inline void emit_i32_add(Register dst, Register lhs, Register rhs);
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inline void emit_i32_add(Register dst, Register lhs, int32_t imm);
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inline void emit_i32_addi(Register dst, Register lhs, int32_t imm);
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inline void emit_i32_sub(Register dst, Register lhs, Register rhs);
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inline void emit_i32_mul(Register dst, Register lhs, Register rhs);
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inline void emit_i32_divs(Register dst, Register lhs, Register rhs,
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@ -528,17 +528,17 @@ class LiftoffAssembler : public TurboAssembler {
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inline void emit_i32_remu(Register dst, Register lhs, Register rhs,
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Label* trap_rem_by_zero);
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inline void emit_i32_and(Register dst, Register lhs, Register rhs);
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inline void emit_i32_and(Register dst, Register lhs, int32_t imm);
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inline void emit_i32_andi(Register dst, Register lhs, int32_t imm);
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inline void emit_i32_or(Register dst, Register lhs, Register rhs);
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inline void emit_i32_or(Register dst, Register lhs, int32_t imm);
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inline void emit_i32_ori(Register dst, Register lhs, int32_t imm);
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inline void emit_i32_xor(Register dst, Register lhs, Register rhs);
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inline void emit_i32_xor(Register dst, Register lhs, int32_t imm);
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inline void emit_i32_xori(Register dst, Register lhs, int32_t imm);
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inline void emit_i32_shl(Register dst, Register src, Register amount);
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inline void emit_i32_shl(Register dst, Register src, int32_t amount);
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inline void emit_i32_shli(Register dst, Register src, int32_t amount);
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inline void emit_i32_sar(Register dst, Register src, Register amount);
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inline void emit_i32_sar(Register dst, Register src, int32_t amount);
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inline void emit_i32_sari(Register dst, Register src, int32_t amount);
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inline void emit_i32_shr(Register dst, Register src, Register amount);
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inline void emit_i32_shr(Register dst, Register src, int32_t amount);
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inline void emit_i32_shri(Register dst, Register src, int32_t amount);
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// i32 unops.
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inline void emit_i32_clz(Register dst, Register src);
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@ -548,8 +548,8 @@ class LiftoffAssembler : public TurboAssembler {
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// i64 binops.
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inline void emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
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LiftoffRegister rhs);
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inline void emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm);
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inline void emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm);
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inline void emit_i64_sub(LiftoffRegister dst, LiftoffRegister lhs,
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LiftoffRegister rhs);
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inline void emit_i64_mul(LiftoffRegister dst, LiftoffRegister lhs,
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@ -565,28 +565,28 @@ class LiftoffAssembler : public TurboAssembler {
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LiftoffRegister rhs, Label* trap_rem_by_zero);
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inline void emit_i64_and(LiftoffRegister dst, LiftoffRegister lhs,
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LiftoffRegister rhs);
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inline void emit_i64_and(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm);
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inline void emit_i64_andi(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm);
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inline void emit_i64_or(LiftoffRegister dst, LiftoffRegister lhs,
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LiftoffRegister rhs);
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inline void emit_i64_or(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm);
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inline void emit_i64_ori(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm);
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inline void emit_i64_xor(LiftoffRegister dst, LiftoffRegister lhs,
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LiftoffRegister rhs);
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inline void emit_i64_xor(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm);
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inline void emit_i64_xori(LiftoffRegister dst, LiftoffRegister lhs,
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int32_t imm);
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inline void emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
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Register amount);
|
||||
inline void emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount);
|
||||
inline void emit_i64_shli(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount);
|
||||
inline void emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
|
||||
Register amount);
|
||||
inline void emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount);
|
||||
inline void emit_i64_sari(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount);
|
||||
inline void emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
|
||||
Register amount);
|
||||
inline void emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount);
|
||||
inline void emit_i64_shri(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount);
|
||||
|
||||
// i64 unops.
|
||||
inline void emit_i64_clz(LiftoffRegister dst, LiftoffRegister src);
|
||||
@ -619,19 +619,19 @@ class LiftoffAssembler : public TurboAssembler {
|
||||
emit_i32_and(dst, lhs, rhs);
|
||||
}
|
||||
}
|
||||
inline void emit_ptrsize_shr(Register dst, Register src, int amount) {
|
||||
inline void emit_ptrsize_shri(Register dst, Register src, int amount) {
|
||||
if (kSystemPointerSize == 8) {
|
||||
emit_i64_shr(LiftoffRegister(dst), LiftoffRegister(src), amount);
|
||||
emit_i64_shri(LiftoffRegister(dst), LiftoffRegister(src), amount);
|
||||
} else {
|
||||
emit_i32_shr(dst, src, amount);
|
||||
emit_i32_shri(dst, src, amount);
|
||||
}
|
||||
}
|
||||
|
||||
inline void emit_ptrsize_add(Register dst, Register lhs, int32_t imm) {
|
||||
inline void emit_ptrsize_addi(Register dst, Register lhs, int32_t imm) {
|
||||
if (kSystemPointerSize == 8) {
|
||||
emit_i64_add(LiftoffRegister(dst), LiftoffRegister(lhs), imm);
|
||||
emit_i64_addi(LiftoffRegister(dst), LiftoffRegister(lhs), imm);
|
||||
} else {
|
||||
emit_i32_add(dst, lhs, imm);
|
||||
emit_i32_addi(dst, lhs, imm);
|
||||
}
|
||||
}
|
||||
|
||||
@ -957,9 +957,9 @@ void LiftoffAssembler::emit_i64_and(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
this, dst, lhs, rhs);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_and(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitI64IndependentHalfOperationImm<&LiftoffAssembler::emit_i32_and>(
|
||||
void LiftoffAssembler::emit_i64_andi(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitI64IndependentHalfOperationImm<&LiftoffAssembler::emit_i32_andi>(
|
||||
this, dst, lhs, imm);
|
||||
}
|
||||
|
||||
@ -969,9 +969,9 @@ void LiftoffAssembler::emit_i64_or(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
this, dst, lhs, rhs);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_or(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitI64IndependentHalfOperationImm<&LiftoffAssembler::emit_i32_or>(
|
||||
void LiftoffAssembler::emit_i64_ori(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitI64IndependentHalfOperationImm<&LiftoffAssembler::emit_i32_ori>(
|
||||
this, dst, lhs, imm);
|
||||
}
|
||||
|
||||
@ -981,9 +981,9 @@ void LiftoffAssembler::emit_i64_xor(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
this, dst, lhs, rhs);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_xor(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitI64IndependentHalfOperationImm<&LiftoffAssembler::emit_i32_xor>(
|
||||
void LiftoffAssembler::emit_i64_xori(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitI64IndependentHalfOperationImm<&LiftoffAssembler::emit_i32_xori>(
|
||||
this, dst, lhs, imm);
|
||||
}
|
||||
|
||||
|
||||
@ -1129,17 +1129,11 @@ class LiftoffCompiler {
|
||||
? __ GetUnusedRegister(result_rc, {lhs})
|
||||
: __ GetUnusedRegister(result_rc);
|
||||
|
||||
fnImm(dst, lhs, imm);
|
||||
CallEmitFn(fnImm, dst, lhs, imm);
|
||||
__ PushRegister(ValueType(result_type), dst);
|
||||
} else {
|
||||
// The RHS was not an immediate.
|
||||
LiftoffRegister rhs = __ PopToRegister();
|
||||
LiftoffRegister lhs = __ PopToRegister(LiftoffRegList::ForRegs(rhs));
|
||||
LiftoffRegister dst = src_rc == result_rc
|
||||
? __ GetUnusedRegister(result_rc, {lhs, rhs})
|
||||
: __ GetUnusedRegister(result_rc);
|
||||
fn(dst, lhs, rhs);
|
||||
__ PushRegister(ValueType(result_type), dst);
|
||||
EmitBinOp<src_type, result_type>(fn);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1187,28 +1181,18 @@ class LiftoffCompiler {
|
||||
case kExpr##opcode: \
|
||||
return EmitBinOp<ValueType::kI32, ValueType::kI32>( \
|
||||
&LiftoffAssembler::emit_##fn);
|
||||
#define CASE_I32_BINOPI(opcode, fn) \
|
||||
case kExpr##opcode: \
|
||||
return EmitBinOpImm<ValueType::kI32, ValueType::kI32>( \
|
||||
[=](LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { \
|
||||
__ emit_##fn(dst.gp(), lhs.gp(), rhs.gp()); \
|
||||
}, \
|
||||
[=](LiftoffRegister dst, LiftoffRegister lhs, int32_t imm) { \
|
||||
__ emit_##fn(dst.gp(), lhs.gp(), imm); \
|
||||
});
|
||||
#define CASE_I32_BINOPI(opcode, fn) \
|
||||
case kExpr##opcode: \
|
||||
return EmitBinOpImm<ValueType::kI32, ValueType::kI32>( \
|
||||
&LiftoffAssembler::emit_##fn, &LiftoffAssembler::emit_##fn##i);
|
||||
#define CASE_I64_BINOP(opcode, fn) \
|
||||
case kExpr##opcode: \
|
||||
return EmitBinOp<ValueType::kI64, ValueType::kI64>( \
|
||||
&LiftoffAssembler::emit_##fn);
|
||||
#define CASE_I64_BINOPI(opcode, fn) \
|
||||
case kExpr##opcode: \
|
||||
return EmitBinOpImm<ValueType::kI64, ValueType::kI64>( \
|
||||
[=](LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { \
|
||||
__ emit_##fn(dst, lhs, rhs); \
|
||||
}, \
|
||||
[=](LiftoffRegister dst, LiftoffRegister lhs, int32_t imm) { \
|
||||
__ emit_##fn(dst, lhs, imm); \
|
||||
});
|
||||
#define CASE_I64_BINOPI(opcode, fn) \
|
||||
case kExpr##opcode: \
|
||||
return EmitBinOpImm<ValueType::kI64, ValueType::kI64>( \
|
||||
&LiftoffAssembler::emit_##fn, &LiftoffAssembler::emit_##fn##i);
|
||||
#define CASE_FLOAT_BINOP(opcode, type, fn) \
|
||||
case kExpr##opcode: \
|
||||
return EmitBinOp<ValueType::k##type, ValueType::k##type>( \
|
||||
@ -1252,9 +1236,7 @@ class LiftoffCompiler {
|
||||
__ emit_##fn(dst, src, \
|
||||
amount.is_gp_pair() ? amount.low_gp() : amount.gp()); \
|
||||
}, \
|
||||
[=](LiftoffRegister dst, LiftoffRegister src, int32_t amount) { \
|
||||
__ emit_##fn(dst, src, amount); \
|
||||
});
|
||||
&LiftoffAssembler::emit_##fn##i);
|
||||
#define CASE_CCALL_BINOP(opcode, type, ext_ref_fn) \
|
||||
case kExpr##opcode: \
|
||||
return EmitBinOp<ValueType::k##type, ValueType::k##type>( \
|
||||
@ -1894,12 +1876,12 @@ class LiftoffCompiler {
|
||||
// AND of two operands. We could introduce a new variant of
|
||||
// {emit_cond_jump} to use the "test" instruction without the "and" here.
|
||||
// Then we can also avoid using the temp register here.
|
||||
__ emit_i32_and(address, index, align_mask);
|
||||
__ emit_i32_andi(address, index, align_mask);
|
||||
__ emit_cond_jump(kUnequal, trap_label, kWasmI32, address);
|
||||
return;
|
||||
}
|
||||
__ emit_i32_add(address, index, offset);
|
||||
__ emit_i32_and(address, address, align_mask);
|
||||
__ emit_i32_addi(address, index, offset);
|
||||
__ emit_i32_andi(address, address, align_mask);
|
||||
|
||||
__ emit_cond_jump(kUnequal, trap_label, kWasmI32, address);
|
||||
}
|
||||
@ -1962,7 +1944,7 @@ class LiftoffCompiler {
|
||||
if (index != old_index) __ Move(index, old_index, kWasmI32);
|
||||
}
|
||||
Register tmp = __ GetUnusedRegister(kGpReg, *pinned).gp();
|
||||
__ emit_ptrsize_add(index, index, *offset);
|
||||
__ emit_ptrsize_addi(index, index, *offset);
|
||||
LOAD_INSTANCE_FIELD(tmp, MemoryMask, kSystemPointerSize);
|
||||
__ emit_ptrsize_and(index, index, tmp);
|
||||
*offset = 0;
|
||||
@ -2046,7 +2028,7 @@ class LiftoffCompiler {
|
||||
void CurrentMemoryPages(FullDecoder* decoder, Value* result) {
|
||||
Register mem_size = __ GetUnusedRegister(kGpReg).gp();
|
||||
LOAD_INSTANCE_FIELD(mem_size, MemorySize, kSystemPointerSize);
|
||||
__ emit_ptrsize_shr(mem_size, mem_size, kWasmPageSizeLog2);
|
||||
__ emit_ptrsize_shri(mem_size, mem_size, kWasmPageSizeLog2);
|
||||
__ PushRegister(kWasmI32, LiftoffRegister(mem_size));
|
||||
}
|
||||
|
||||
@ -2219,7 +2201,7 @@ class LiftoffCompiler {
|
||||
// 3) mask = diff & neg_index
|
||||
__ emit_i32_and(mask, diff, neg_index);
|
||||
// 4) mask = mask >> 31
|
||||
__ emit_i32_sar(mask, mask, 31);
|
||||
__ emit_i32_sari(mask, mask, 31);
|
||||
|
||||
// Apply mask.
|
||||
__ emit_i32_and(index, index, mask);
|
||||
@ -2230,7 +2212,7 @@ class LiftoffCompiler {
|
||||
LOAD_INSTANCE_FIELD(table, IndirectFunctionTableSigIds, kSystemPointerSize);
|
||||
// Shift {index} by 2 (multiply by 4) to represent kInt32Size items.
|
||||
STATIC_ASSERT((1 << 2) == kInt32Size);
|
||||
__ emit_i32_shl(index, index, 2);
|
||||
__ emit_i32_shli(index, index, 2);
|
||||
__ Load(LiftoffRegister(scratch), table, index, 0, LoadType::kI32Load,
|
||||
pinned);
|
||||
|
||||
@ -2652,7 +2634,7 @@ class LiftoffCompiler {
|
||||
|
||||
uint32_t offset = imm.offset;
|
||||
index_reg = AddMemoryMasking(index_reg, &offset, &pinned);
|
||||
if (offset != 0) __ emit_i32_add(index_reg, index_reg, offset);
|
||||
if (offset != 0) __ emit_i32_addi(index_reg, index_reg, offset);
|
||||
|
||||
LiftoffAssembler::VarState timeout =
|
||||
__ cache_state()->stack_state.end()[-1];
|
||||
@ -2722,7 +2704,7 @@ class LiftoffCompiler {
|
||||
|
||||
uint32_t offset = imm.offset;
|
||||
index = AddMemoryMasking(index, &offset, &pinned);
|
||||
if (offset) __ emit_i32_add(index, index, offset);
|
||||
if (offset) __ emit_i32_addi(index, index, offset);
|
||||
|
||||
// TODO(ahaas): Use PrepareCall to prepare parameters.
|
||||
__ SpillAllRegisters();
|
||||
|
||||
@ -768,10 +768,10 @@ I32_BINOP(xor, xor_)
|
||||
|
||||
#undef I32_BINOP
|
||||
|
||||
#define I32_BINOP_I(name, instruction) \
|
||||
void LiftoffAssembler::emit_i32_##name(Register dst, Register lhs, \
|
||||
int32_t imm) { \
|
||||
instruction(dst, lhs, Operand(imm)); \
|
||||
#define I32_BINOP_I(name, instruction) \
|
||||
void LiftoffAssembler::emit_i32_##name##i(Register dst, Register lhs, \
|
||||
int32_t imm) { \
|
||||
instruction(dst, lhs, Operand(imm)); \
|
||||
}
|
||||
|
||||
// clang-format off
|
||||
@ -816,8 +816,8 @@ I32_SHIFTOP_I(shr, srl)
|
||||
#undef I32_SHIFTOP
|
||||
#undef I32_SHIFTOP_I
|
||||
|
||||
void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
void LiftoffAssembler::emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
TurboAssembler::AddPair(dst.low_gp(), dst.high_gp(), lhs.low_gp(),
|
||||
lhs.high_gp(), imm,
|
||||
kScratchReg, kScratchReg2);
|
||||
@ -922,8 +922,8 @@ void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
|
||||
&TurboAssembler::ShlPair);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i64_shli(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
UseScratchRegisterScope temps(this);
|
||||
// {src.low_gp()} will still be needed after writing {dst.high_gp()} and
|
||||
// {dst.low_gp()}.
|
||||
@ -946,8 +946,8 @@ void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
|
||||
&TurboAssembler::SarPair);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i64_sari(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
UseScratchRegisterScope temps(this);
|
||||
// {src.high_gp()} will still be needed after writing {dst.high_gp()} and
|
||||
// {dst.low_gp()}.
|
||||
@ -965,8 +965,8 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
|
||||
&TurboAssembler::ShrPair);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i64_shri(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
UseScratchRegisterScope temps(this);
|
||||
// {src.high_gp()} will still be needed after writing {dst.high_gp()} and
|
||||
// {dst.low_gp()}.
|
||||
|
||||
@ -264,22 +264,22 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
|
||||
Register rhs) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 binop:: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_I32_BINOP_I(name) \
|
||||
UNIMPLEMENTED_I32_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register lhs, \
|
||||
int32_t imm) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 binop_i: " #name); \
|
||||
#define UNIMPLEMENTED_I32_BINOP_I(name) \
|
||||
UNIMPLEMENTED_I32_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name##i(Register dst, Register lhs, \
|
||||
int32_t imm) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 binop_i: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_I64_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
|
||||
LiftoffRegister rhs) { \
|
||||
bailout(kUnsupportedArchitecture, "i64 binop: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_I64_BINOP_I(name) \
|
||||
UNIMPLEMENTED_I64_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
|
||||
int32_t imm) { \
|
||||
bailout(kUnsupportedArchitecture, "i64_i binop: " #name); \
|
||||
#define UNIMPLEMENTED_I64_BINOP_I(name) \
|
||||
UNIMPLEMENTED_I64_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name##i(LiftoffRegister dst, \
|
||||
LiftoffRegister lhs, int32_t imm) { \
|
||||
bailout(kUnsupportedArchitecture, "i64_i binop: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_GP_UNOP(name) \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register src) { \
|
||||
@ -299,22 +299,22 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
|
||||
bailout(kUnsupportedArchitecture, "fp unop: " #name); \
|
||||
return true; \
|
||||
}
|
||||
#define UNIMPLEMENTED_I32_SHIFTOP(name) \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register src, \
|
||||
Register amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 shiftop: " #name); \
|
||||
} \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register src, \
|
||||
int32_t amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 shiftop: " #name); \
|
||||
#define UNIMPLEMENTED_I32_SHIFTOP(name) \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register src, \
|
||||
Register amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 shiftop: " #name); \
|
||||
} \
|
||||
void LiftoffAssembler::emit_##name##i(Register dst, Register src, \
|
||||
int32_t amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 shiftop: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_I64_SHIFTOP(name) \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister src, \
|
||||
Register amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i64 shiftop: " #name); \
|
||||
} \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister src, \
|
||||
int32_t amount) { \
|
||||
void LiftoffAssembler::emit_##name##i(LiftoffRegister dst, \
|
||||
LiftoffRegister src, int32_t amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i64 shiftop: " #name); \
|
||||
}
|
||||
|
||||
|
||||
@ -268,22 +268,22 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
|
||||
Register rhs) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 binop: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_I32_BINOP_I(name) \
|
||||
UNIMPLEMENTED_I32_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register lhs, \
|
||||
int32_t imm) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 binop_i: " #name); \
|
||||
#define UNIMPLEMENTED_I32_BINOP_I(name) \
|
||||
UNIMPLEMENTED_I32_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name##i(Register dst, Register lhs, \
|
||||
int32_t imm) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 binop_i: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_I64_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
|
||||
LiftoffRegister rhs) { \
|
||||
bailout(kUnsupportedArchitecture, "i64 binop: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_I64_BINOP_I(name) \
|
||||
UNIMPLEMENTED_I64_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
|
||||
int32_t imm) { \
|
||||
bailout(kUnsupportedArchitecture, "i64 binop_i: " #name); \
|
||||
#define UNIMPLEMENTED_I64_BINOP_I(name) \
|
||||
UNIMPLEMENTED_I64_BINOP(name) \
|
||||
void LiftoffAssembler::emit_##name##i(LiftoffRegister dst, \
|
||||
LiftoffRegister lhs, int32_t imm) { \
|
||||
bailout(kUnsupportedArchitecture, "i64 binop_i: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_GP_UNOP(name) \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register src) { \
|
||||
@ -303,22 +303,22 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
|
||||
bailout(kUnsupportedArchitecture, "fp unop: " #name); \
|
||||
return true; \
|
||||
}
|
||||
#define UNIMPLEMENTED_I32_SHIFTOP(name) \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register src, \
|
||||
Register amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 shiftop: " #name); \
|
||||
} \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register src, \
|
||||
int32_t amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 shiftop: " #name); \
|
||||
#define UNIMPLEMENTED_I32_SHIFTOP(name) \
|
||||
void LiftoffAssembler::emit_##name(Register dst, Register src, \
|
||||
Register amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 shiftop: " #name); \
|
||||
} \
|
||||
void LiftoffAssembler::emit_##name##i(Register dst, Register src, \
|
||||
int32_t amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i32 shiftop: " #name); \
|
||||
}
|
||||
#define UNIMPLEMENTED_I64_SHIFTOP(name) \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister src, \
|
||||
Register amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i64 shiftop: " #name); \
|
||||
} \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister src, \
|
||||
int32_t amount) { \
|
||||
void LiftoffAssembler::emit_##name##i(LiftoffRegister dst, \
|
||||
LiftoffRegister src, int32_t amount) { \
|
||||
bailout(kUnsupportedArchitecture, "i64 shiftop: " #name); \
|
||||
}
|
||||
|
||||
|
||||
@ -840,7 +840,7 @@ void LiftoffAssembler::emit_i32_add(Register dst, Register lhs, Register rhs) {
|
||||
}
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32_add(Register dst, Register lhs, int32_t imm) {
|
||||
void LiftoffAssembler::emit_i32_addi(Register dst, Register lhs, int32_t imm) {
|
||||
if (lhs != dst) {
|
||||
leal(dst, Operand(lhs, imm));
|
||||
} else {
|
||||
@ -1006,7 +1006,7 @@ void LiftoffAssembler::emit_i32_and(Register dst, Register lhs, Register rhs) {
|
||||
lhs, rhs);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32_and(Register dst, Register lhs, int32_t imm) {
|
||||
void LiftoffAssembler::emit_i32_andi(Register dst, Register lhs, int32_t imm) {
|
||||
liftoff::EmitCommutativeBinOpImm<&Assembler::andl, &Assembler::movl>(
|
||||
this, dst, lhs, imm);
|
||||
}
|
||||
@ -1016,7 +1016,7 @@ void LiftoffAssembler::emit_i32_or(Register dst, Register lhs, Register rhs) {
|
||||
lhs, rhs);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32_or(Register dst, Register lhs, int32_t imm) {
|
||||
void LiftoffAssembler::emit_i32_ori(Register dst, Register lhs, int32_t imm) {
|
||||
liftoff::EmitCommutativeBinOpImm<&Assembler::orl, &Assembler::movl>(this, dst,
|
||||
lhs, imm);
|
||||
}
|
||||
@ -1026,7 +1026,7 @@ void LiftoffAssembler::emit_i32_xor(Register dst, Register lhs, Register rhs) {
|
||||
lhs, rhs);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32_xor(Register dst, Register lhs, int32_t imm) {
|
||||
void LiftoffAssembler::emit_i32_xori(Register dst, Register lhs, int32_t imm) {
|
||||
liftoff::EmitCommutativeBinOpImm<&Assembler::xorl, &Assembler::movl>(
|
||||
this, dst, lhs, imm);
|
||||
}
|
||||
@ -1071,8 +1071,8 @@ void LiftoffAssembler::emit_i32_shl(Register dst, Register src,
|
||||
&Assembler::shll_cl);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32_shl(Register dst, Register src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i32_shli(Register dst, Register src,
|
||||
int32_t amount) {
|
||||
if (dst != src) movl(dst, src);
|
||||
shll(dst, Immediate(amount & 31));
|
||||
}
|
||||
@ -1083,8 +1083,8 @@ void LiftoffAssembler::emit_i32_sar(Register dst, Register src,
|
||||
&Assembler::sarl_cl);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32_sar(Register dst, Register src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i32_sari(Register dst, Register src,
|
||||
int32_t amount) {
|
||||
if (dst != src) movl(dst, src);
|
||||
sarl(dst, Immediate(amount & 31));
|
||||
}
|
||||
@ -1095,8 +1095,8 @@ void LiftoffAssembler::emit_i32_shr(Register dst, Register src,
|
||||
&Assembler::shrl_cl);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32_shr(Register dst, Register src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i32_shri(Register dst, Register src,
|
||||
int32_t amount) {
|
||||
if (dst != src) movl(dst, src);
|
||||
shrl(dst, Immediate(amount & 31));
|
||||
}
|
||||
@ -1125,8 +1125,8 @@ void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
}
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
void LiftoffAssembler::emit_i64_addi(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
if (lhs.gp() != dst.gp()) {
|
||||
leaq(dst.gp(), Operand(lhs.gp(), imm));
|
||||
} else {
|
||||
@ -1191,8 +1191,8 @@ void LiftoffAssembler::emit_i64_and(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
this, dst.gp(), lhs.gp(), rhs.gp());
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_and(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
void LiftoffAssembler::emit_i64_andi(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitCommutativeBinOpImm<&Assembler::andq, &Assembler::movq>(
|
||||
this, dst.gp(), lhs.gp(), imm);
|
||||
}
|
||||
@ -1203,8 +1203,8 @@ void LiftoffAssembler::emit_i64_or(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
this, dst.gp(), lhs.gp(), rhs.gp());
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_or(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
void LiftoffAssembler::emit_i64_ori(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitCommutativeBinOpImm<&Assembler::orq, &Assembler::movq>(
|
||||
this, dst.gp(), lhs.gp(), imm);
|
||||
}
|
||||
@ -1215,8 +1215,8 @@ void LiftoffAssembler::emit_i64_xor(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
this, dst.gp(), lhs.gp(), rhs.gp());
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_xor(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
void LiftoffAssembler::emit_i64_xori(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
int32_t imm) {
|
||||
liftoff::EmitCommutativeBinOpImm<&Assembler::xorq, &Assembler::movq>(
|
||||
this, dst.gp(), lhs.gp(), imm);
|
||||
}
|
||||
@ -1227,8 +1227,8 @@ void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
|
||||
&Assembler::shlq_cl);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_shl(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i64_shli(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
if (dst.gp() != src.gp()) movq(dst.gp(), src.gp());
|
||||
shlq(dst.gp(), Immediate(amount & 63));
|
||||
}
|
||||
@ -1239,8 +1239,8 @@ void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
|
||||
&Assembler::sarq_cl);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_sar(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i64_sari(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
if (dst.gp() != src.gp()) movq(dst.gp(), src.gp());
|
||||
sarq(dst.gp(), Immediate(amount & 63));
|
||||
}
|
||||
@ -1251,8 +1251,8 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
|
||||
&Assembler::shrq_cl);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
void LiftoffAssembler::emit_i64_shri(LiftoffRegister dst, LiftoffRegister src,
|
||||
int32_t amount) {
|
||||
if (dst != src) movq(dst.gp(), src.gp());
|
||||
shrq(dst.gp(), Immediate(amount & 63));
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user