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Revert of [turbofan] Implemented the TruncateFloat32ToInt64 TurboFan operator. (patchset #1 id:1 of https://codereview.chromium.org/1476063002/ )

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Reason for revert:
Unexpected error occurred.

Original issue's description:
> [turbofan] Implemented the TruncateFloat32ToInt64 TurboFan operator.
>
> The TruncateFloat32ToInt64 operator converts a float32 to an int64 using
> the round-to-zero rounding mode (truncate). If the input value is
> outside the int64 range, then the result depends on the architecture. I
> implemented the operator on x64, arm64, and mips64.
>
> R=titzer@chromium.org, jacob.bramley@arm.com
>
> Committed: https://crrev.com/1df1066c3c77464d2a68d7c8d501a5a0f3ad195a
> Cr-Commit-Position: refs/heads/master@{#32315}

TBR=jacob.bramley@arm.com,titzer@chromium.org,v8-mips-ports@googlegroups.com
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true

Review URL: https://codereview.chromium.org/1475343002

Cr-Commit-Position: refs/heads/master@{#32316}
This commit is contained in:
ahaas 2015-11-26 01:05:50 -08:00 committed by Commit bot
parent 1df1066c3c
commit a336404f61
23 changed files with 0 additions and 137 deletions
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3
src/compiler/arm64/code-generator-arm64.cc
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@ -1022,9 +1022,6 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
case kArm64Float64ToUint32:
__ Fcvtzu(i.OutputRegister32(), i.InputDoubleRegister(0));
break;
case kArm64Float32ToInt64:
__ Fcvtzs(i.OutputRegister64(), i.InputFloat32Register(0));
break;
case kArm64Float64ToInt64:
__ Fcvtzs(i.OutputRegister64(), i.InputDoubleRegister(0));
break;

1
src/compiler/arm64/instruction-codes-arm64.h
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@ -112,7 +112,6 @@ namespace compiler {
V(Arm64Float64ToFloat32) \
V(Arm64Float64ToInt32) \
V(Arm64Float64ToUint32) \
V(Arm64Float32ToInt64) \
V(Arm64Float64ToInt64) \
V(Arm64Float64ToUint64) \
V(Arm64Int32ToFloat64) \

5
src/compiler/arm64/instruction-selector-arm64.cc
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@ -1237,11 +1237,6 @@ void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
}
void InstructionSelector::VisitTruncateFloat32ToInt64(Node* node) {
VisitRR(this, kArm64Float32ToInt64, node);
}
void InstructionSelector::VisitTruncateFloat64ToInt64(Node* node) {
VisitRR(this, kArm64Float64ToInt64, node);
}

7
src/compiler/instruction-selector.cc
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@ -847,8 +847,6 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsWord32(node), VisitChangeFloat64ToInt32(node);
case IrOpcode::kChangeFloat64ToUint32:
return MarkAsWord32(node), VisitChangeFloat64ToUint32(node);
case IrOpcode::kTruncateFloat32ToInt64:
return MarkAsWord64(node), VisitTruncateFloat32ToInt64(node);
case IrOpcode::kTruncateFloat64ToInt64:
return MarkAsWord64(node), VisitTruncateFloat64ToInt64(node);
case IrOpcode::kTruncateFloat64ToUint64:
@ -1101,11 +1099,6 @@ void InstructionSelector::VisitChangeUint32ToUint64(Node* node) {
}
void InstructionSelector::VisitTruncateFloat32ToInt64(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitTruncateFloat64ToInt64(Node* node) {
UNIMPLEMENTED();
}

1
src/compiler/machine-operator.cc
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@ -135,7 +135,6 @@ CheckedStoreRepresentation CheckedStoreRepresentationOf(Operator const* op) {
V(ChangeFloat32ToFloat64, Operator::kNoProperties, 1, 0, 1) \
V(ChangeFloat64ToInt32, Operator::kNoProperties, 1, 0, 1) \
V(ChangeFloat64ToUint32, Operator::kNoProperties, 1, 0, 1) \
V(TruncateFloat32ToInt64, Operator::kNoProperties, 1, 0, 1) \
V(TruncateFloat64ToInt64, Operator::kNoProperties, 1, 0, 1) \
V(TruncateFloat64ToUint64, Operator::kNoProperties, 1, 0, 1) \
V(ChangeInt32ToFloat64, Operator::kNoProperties, 1, 0, 1) \

1
src/compiler/machine-operator.h
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@ -207,7 +207,6 @@ class MachineOperatorBuilder final : public ZoneObject {
const Operator* ChangeFloat32ToFloat64();
const Operator* ChangeFloat64ToInt32(); // narrowing
const Operator* ChangeFloat64ToUint32(); // narrowing
const Operator* TruncateFloat32ToInt64();
const Operator* TruncateFloat64ToInt64();
const Operator* TruncateFloat64ToUint64();
const Operator* ChangeInt32ToFloat64();

7
src/compiler/mips64/code-generator-mips64.cc
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@ -991,13 +991,6 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ mfc1(i.OutputRegister(), scratch);
break;
}
case kMips64TruncLS: {
FPURegister scratch = kScratchDoubleReg;
// Other arches use round to zero here, so we follow.
__ trunc_l_s(scratch, i.InputDoubleRegister(0));
__ dmfc1(i.OutputRegister(), scratch);
break;
}
case kMips64TruncLD: {
FPURegister scratch = kScratchDoubleReg;
// Other arches use round to zero here, so we follow.

1
src/compiler/mips64/instruction-codes-mips64.h
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@ -75,7 +75,6 @@ namespace compiler {
V(Mips64CvtSD) \
V(Mips64CvtDS) \
V(Mips64TruncWD) \
V(Mips64TruncLS) \
V(Mips64TruncLD) \
V(Mips64TruncUwD) \
V(Mips64TruncUlD) \

5
src/compiler/mips64/instruction-selector-mips64.cc
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@ -731,11 +731,6 @@ void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
}
void InstructionSelector::VisitTruncateFloat32ToInt64(Node* node) {
VisitRR(this, kMips64TruncLS, node);
}
void InstructionSelector::VisitTruncateFloat64ToInt64(Node* node) {
VisitRR(this, kMips64TruncLD, node);
}

1
src/compiler/opcodes.h
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@ -270,7 +270,6 @@
V(ChangeFloat32ToFloat64) \
V(ChangeFloat64ToInt32) \
V(ChangeFloat64ToUint32) \
V(TruncateFloat32ToInt64) \
V(TruncateFloat64ToInt64) \
V(TruncateFloat64ToUint64) \
V(ChangeInt32ToFloat64) \

5
src/compiler/ppc/instruction-selector-ppc.cc
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@ -927,11 +927,6 @@ void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
#if V8_TARGET_ARCH_PPC64
void InstructionSelector::VisitTruncateFloat32ToInt64(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitTruncateFloat64ToInt64(Node* node) {
VisitRR(this, kPPC_DoubleToInt64, node);
}

3
src/compiler/raw-machine-assembler.h
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@ -438,9 +438,6 @@ class RawMachineAssembler {
Node* ChangeFloat64ToUint32(Node* a) {
return AddNode(machine()->ChangeFloat64ToUint32(), a);
}
Node* TruncateFloat32ToInt64(Node* a) {
return AddNode(machine()->TruncateFloat32ToInt64(), a);
}
Node* TruncateFloat64ToInt64(Node* a) {
return AddNode(machine()->TruncateFloat64ToInt64(), a);
}

5
src/compiler/typer.cc
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@ -2102,11 +2102,6 @@ Type* Typer::Visitor::TypeChangeFloat64ToUint32(Node* node) {
}
Type* Typer::Visitor::TypeTruncateFloat32ToInt64(Node* node) {
return Type::Internal();
}
Type* Typer::Visitor::TypeTruncateFloat64ToInt64(Node* node) {
return Type::Internal();
}

1
src/compiler/verifier.cc
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@ -919,7 +919,6 @@ void Verifier::Visitor::Check(Node* node) {
case IrOpcode::kChangeFloat32ToFloat64:
case IrOpcode::kChangeFloat64ToInt32:
case IrOpcode::kChangeFloat64ToUint32:
case IrOpcode::kTruncateFloat32ToInt64:
case IrOpcode::kTruncateFloat64ToInt64:
case IrOpcode::kTruncateFloat64ToUint64:
case IrOpcode::kFloat64ExtractLowWord32:

7
src/compiler/x64/code-generator-x64.cc
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@ -1043,13 +1043,6 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ AssertZeroExtended(i.OutputRegister());
break;
}
case kSSEFloat32ToInt64:
if (instr->InputAt(0)->IsDoubleRegister()) {
__ Cvttss2siq(i.OutputRegister(), i.InputDoubleRegister(0));
} else {
__ Cvttss2siq(i.OutputRegister(), i.InputOperand(0));
}
break;
case kSSEFloat64ToInt64:
if (instr->InputAt(0)->IsDoubleRegister()) {
__ Cvttsd2siq(i.OutputRegister(), i.InputDoubleRegister(0));

1
src/compiler/x64/instruction-codes-x64.h
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@ -79,7 +79,6 @@ namespace compiler {
V(SSEFloat64ToFloat32) \
V(SSEFloat64ToInt32) \
V(SSEFloat64ToUint32) \
V(SSEFloat32ToInt64) \
V(SSEFloat64ToInt64) \
V(SSEFloat64ToUint64) \
V(SSEInt32ToFloat64) \

6
src/compiler/x64/instruction-selector-x64.cc
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@ -834,12 +834,6 @@ void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
}
void InstructionSelector::VisitTruncateFloat32ToInt64(Node* node) {
X64OperandGenerator g(this);
Emit(kSSEFloat32ToInt64, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}
void InstructionSelector::VisitTruncateFloat64ToInt64(Node* node) {
X64OperandGenerator g(this);
Emit(kSSEFloat64ToInt64, g.DefineAsRegister(node), g.Use(node->InputAt(0)));

22
src/x64/assembler-x64.cc
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@ -3112,28 +3112,6 @@ void Assembler::cvttsd2si(Register dst, XMMRegister src) {
}
void Assembler::cvttss2siq(Register dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
emit_rex_64(dst, src);
emit(0x0F);
emit(0x2C);
emit_sse_operand(dst, src);
}
void Assembler::cvttss2siq(Register dst, const Operand& src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
emit_rex_64(dst, src);
emit(0x0F);
emit(0x2C);
emit_sse_operand(dst, src);
}
void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);

10
src/x64/assembler-x64.h
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@ -1077,8 +1077,6 @@ class Assembler : public AssemblerBase {
void cvttsd2si(Register dst, const Operand& src);
void cvttsd2si(Register dst, XMMRegister src);
void cvttss2siq(Register dst, XMMRegister src);
void cvttss2siq(Register dst, const Operand& src);
void cvttsd2siq(Register dst, XMMRegister src);
void cvttsd2siq(Register dst, const Operand& src);
@ -1392,14 +1390,6 @@ class Assembler : public AssemblerBase {
XMMRegister idst = {dst.code()};
vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0);
}
void vcvttss2siq(Register dst, XMMRegister src) {
XMMRegister idst = {dst.code()};
vsd(0x2c, idst, xmm0, src, kF3, k0F, kW1);
}
void vcvttss2siq(Register dst, const Operand& src) {
XMMRegister idst = {dst.code()};
vsd(0x2c, idst, xmm0, src, kF3, k0F, kW1);
}
void vcvttsd2siq(Register dst, XMMRegister src) {
XMMRegister idst = {dst.code()};
vsd(0x2c, idst, xmm0, src, kF2, k0F, kW1);

5
src/x64/disasm-x64.cc
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@ -989,11 +989,6 @@ int DisassemblerX64::AVXInstruction(byte* data) {
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightOperand(current);
break;
case 0x2c:
AppendToBuffer("vcvttss2si%s %s,", vex_w() ? "q" : "",
NameOfCPURegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x58:
AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));

20
src/x64/macro-assembler-x64.cc
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@ -967,26 +967,6 @@ void MacroAssembler::Cvttsd2si(Register dst, const Operand& src) {
}
void MacroAssembler::Cvttss2siq(Register dst, XMMRegister src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vcvttss2siq(dst, src);
} else {
cvttss2siq(dst, src);
}
}
void MacroAssembler::Cvttss2siq(Register dst, const Operand& src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vcvttss2siq(dst, src);
} else {
cvttss2siq(dst, src);
}
}
void MacroAssembler::Cvttsd2siq(Register dst, XMMRegister src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);

2
src/x64/macro-assembler-x64.h
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@ -832,8 +832,6 @@ class MacroAssembler: public Assembler {
void Cvttsd2si(Register dst, XMMRegister src);
void Cvttsd2si(Register dst, const Operand& src);
void Cvttss2siq(Register dst, XMMRegister src);
void Cvttss2siq(Register dst, const Operand& src);
void Cvttsd2siq(Register dst, XMMRegister src);
void Cvttsd2siq(Register dst, const Operand& src);

18
test/cctest/compiler/test-run-machops.cc
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@ -5391,24 +5391,6 @@ TEST(RunBitcastFloat64ToInt64) {
}
TEST(RunTruncateFloat32ToInt64) {
BufferedRawMachineAssemblerTester<int64_t> m(kMachFloat32);
m.Return(m.TruncateFloat32ToInt64(m.Parameter(0)));
FOR_INT64_INPUTS(i) {
float input = static_cast<float>(*i);
if (input < 9223372036854775808.0 && input > -9223372036854775809.0) {
CHECK_EQ(static_cast<int64_t>(input), m.Call(input));
}
}
FOR_FLOAT32_INPUTS(j) {
if (*j < 9223372036854775808.0 && *j > -9223372036854775809.0) {
CHECK_EQ(static_cast<int64_t>(*j), m.Call(*j));
}
}
}
TEST(RunTruncateFloat64ToInt64) {
BufferedRawMachineAssemblerTester<int64_t> m(kMachFloat64);
m.Return(m.TruncateFloat64ToInt64(m.Parameter(0)));