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S390[liftoff]: refactor simd relaxed ops

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Cleanup the emitters by using non-relaxed simd ops.

Change-Id: I079d999ee5bb194c538ad7c4b0192ac552b1b601
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4184556
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Reviewed-by: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/main@{#85440}
This commit is contained in:
Milad Fa 2023-01-20 11:21:45 -05:00 committed by V8 LUCI CQ
parent 78addf2f16
commit a41eb50499
1 changed files with 39 additions and 76 deletions
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115
src/wasm/baseline/s390/liftoff-assembler-s390.h
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@ -2658,6 +2658,38 @@ SIMD_QFM_LIST(EMIT_SIMD_QFM)
#undef EMIT_SIMD_QFM
#undef SIMD_QFM_LIST
#define SIMD_RELAXED_BINOP_LIST(V) \
V(i8x16_relaxed_swizzle, i8x16_swizzle) \
V(f64x2_relaxed_min, f64x2_pmin) \
V(f64x2_relaxed_max, f64x2_pmax) \
V(f32x4_relaxed_min, f32x4_pmin) \
V(f32x4_relaxed_max, f32x4_pmax) \
V(i16x8_relaxed_q15mulr_s, i16x8_q15mulr_sat_s)
#define SIMD_VISIT_RELAXED_BINOP(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
LiftoffRegister rhs) { \
emit_##op(dst, lhs, rhs); \
}
SIMD_RELAXED_BINOP_LIST(SIMD_VISIT_RELAXED_BINOP)
#undef SIMD_VISIT_RELAXED_BINOP
#undef SIMD_RELAXED_BINOP_LIST
#define SIMD_RELAXED_UNOP_LIST(V) \
V(i32x4_relaxed_trunc_f32x4_s, i32x4_sconvert_f32x4) \
V(i32x4_relaxed_trunc_f32x4_u, i32x4_uconvert_f32x4) \
V(i32x4_relaxed_trunc_f64x2_s_zero, i32x4_trunc_sat_f64x2_s_zero) \
V(i32x4_relaxed_trunc_f64x2_u_zero, i32x4_trunc_sat_f64x2_u_zero)
#define SIMD_VISIT_RELAXED_UNOP(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, \
LiftoffRegister src) { \
emit_##op(dst, src); \
}
SIMD_RELAXED_UNOP_LIST(SIMD_VISIT_RELAXED_UNOP)
#undef SIMD_VISIT_RELAXED_UNOP
#undef SIMD_RELAXED_UNOP_LIST
void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
Register offset_reg, uintptr_t offset_imm,
LoadType type,
@ -2804,68 +2836,6 @@ void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst,
I8x16Swizzle(dest, src1, src2, r0, r1, kScratchDoubleReg, temp);
}
void LiftoffAssembler::emit_i8x16_relaxed_swizzle(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
Simd128Register src1 = lhs.fp();
Simd128Register src2 = rhs.fp();
Simd128Register dest = dst.fp();
Simd128Register temp =
GetUnusedRegister(kFpReg, LiftoffRegList{dest, src1, src2}).fp();
I8x16Swizzle(dest, src1, src2, r0, r1, kScratchDoubleReg, temp);
}
void LiftoffAssembler::emit_i32x4_relaxed_trunc_f32x4_s(LiftoffRegister dst,
LiftoffRegister src) {
I32x4SConvertF32x4(dst.fp(), src.fp(), kScratchDoubleReg, r0);
}
void LiftoffAssembler::emit_i32x4_relaxed_trunc_f32x4_u(LiftoffRegister dst,
LiftoffRegister src) {
I32x4UConvertF32x4(dst.fp(), src.fp(), kScratchDoubleReg, r0);
}
void LiftoffAssembler::emit_i32x4_relaxed_trunc_f64x2_s_zero(
LiftoffRegister dst, LiftoffRegister src) {
emit_i32x4_trunc_sat_f64x2_s_zero(dst, src);
}
void LiftoffAssembler::emit_i32x4_relaxed_trunc_f64x2_u_zero(
LiftoffRegister dst, LiftoffRegister src) {
emit_i32x4_trunc_sat_f64x2_u_zero(dst, src);
}
void LiftoffAssembler::emit_s128_relaxed_laneselect(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
LiftoffRegister mask) {
emit_s128_select(dst, src1, src2, mask);
}
void LiftoffAssembler::emit_f64x2_relaxed_min(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
emit_f64x2_pmin(dst, lhs, rhs);
}
void LiftoffAssembler::emit_f64x2_relaxed_max(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
emit_f64x2_pmax(dst, lhs, rhs);
}
void LiftoffAssembler::emit_f32x4_relaxed_min(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
emit_f32x4_pmin(dst, lhs, rhs);
}
void LiftoffAssembler::emit_f32x4_relaxed_max(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
emit_f32x4_pmax(dst, lhs, rhs);
}
void LiftoffAssembler::emit_f64x2_convert_low_i32x4_s(LiftoffRegister dst,
LiftoffRegister src) {
F64x2ConvertLowI32x4S(dst.fp(), src.fp());
@ -2916,20 +2886,6 @@ void LiftoffAssembler::emit_i16x8_q15mulr_sat_s(LiftoffRegister dst,
I16x8Q15MulRSatS(dest, s1, s2, kScratchDoubleReg, temp1, temp2);
}
void LiftoffAssembler::emit_i16x8_relaxed_q15mulr_s(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2) {
Simd128Register s1 = src1.fp();
Simd128Register s2 = src2.fp();
Simd128Register dest = dst.fp();
// Make sure temp registers are unique.
Simd128Register temp1 =
GetUnusedRegister(kFpReg, LiftoffRegList{dest, s1, s2}).fp();
Simd128Register temp2 =
GetUnusedRegister(kFpReg, LiftoffRegList{dest, s1, s2, temp1}).fp();
I16x8Q15MulRSatS(dest, s1, s2, kScratchDoubleReg, temp1, temp2);
}
void LiftoffAssembler::emit_i16x8_dot_i8x16_i7x16_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
@ -3062,6 +3018,13 @@ void LiftoffAssembler::emit_i32x4_trunc_sat_f64x2_u_zero(LiftoffRegister dst,
I32x4TruncSatF64x2UZero(dst.fp(), src.fp(), kScratchDoubleReg);
}
void LiftoffAssembler::emit_s128_relaxed_laneselect(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
LiftoffRegister mask) {
emit_s128_select(dst, src1, src2, mask);
}
void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) {
LoadU64(limit_address, MemOperand(limit_address));
CmpU64(sp, limit_address);