AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

Validate that instruction selection maintains SSA form.

Browse Source 
It benefits certain algorithms in register allocation to assume the input is
SSA - understanding that ResolvePhis in the regalloc pipeline lowers
phis, thus blurring the SSA invariant.

BUG=

Review URL: https://codereview.chromium.org/1760323002

Cr-Commit-Position: refs/heads/master@{#34509}
This commit is contained in:
mtrofin 2016-03-04 12:32:34 -08:00 committed by Commit bot
parent 35bce027d2
commit a59605efda
3 changed files with 22 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/compiler/instruction-selector.cc
View File

@ -82,6 +82,9 @@ void InstructionSelector::SelectInstructions() {
}
EndBlock(RpoNumber::FromInt(block->rpo_number()));
}
#if DEBUG
sequence()->ValidateSSA();
#endif
}

19
src/compiler/instruction.cc
View File

@ -620,7 +620,7 @@ InstructionBlocks* InstructionSequence::InstructionBlocksFor(
return blocks;
}
void InstructionSequence::Validate() {
void InstructionSequence::ValidateEdgeSplitForm() {
// Validate blocks are in edge-split form: no block with multiple successors
// has an edge to a block (== a successor) with more than one predecessors.
for (const InstructionBlock* block : instruction_blocks()) {
@ -635,6 +635,21 @@ void InstructionSequence::Validate() {
}
}
void InstructionSequence::ValidateSSA() {
// TODO(mtrofin): We could use a local zone here instead.
BitVector definitions(VirtualRegisterCount(), zone());
for (const Instruction* instruction : *this) {
for (size_t i = 0; i < instruction->OutputCount(); ++i) {
const InstructionOperand* output = instruction->OutputAt(i);
int vreg = (output->IsConstant())
? ConstantOperand::cast(output)->virtual_register()
: UnallocatedOperand::cast(output)->virtual_register();
CHECK(!definitions.Contains(vreg));
definitions.Add(vreg);
}
}
}
void InstructionSequence::ComputeAssemblyOrder(InstructionBlocks* blocks) {
int ao = 0;
for (InstructionBlock* const block : *blocks) {
@ -669,7 +684,7 @@ InstructionSequence::InstructionSequence(Isolate* isolate,
block_starts_.reserve(instruction_blocks_->size());
#if DEBUG
Validate();
ValidateEdgeSplitForm();
#endif
}

3
src/compiler/instruction.h
View File

@ -1354,7 +1354,8 @@ class InstructionSequence final : public ZoneObject {
void PrintBlock(const RegisterConfiguration* config, int block_id) const;
void PrintBlock(int block_id) const;
void Validate();
void ValidateEdgeSplitForm();
void ValidateSSA();
private:
friend std::ostream& operator<<(std::ostream& os,