X87: [turbofan] Support subtraction displacements in BaseWithIndexAndDisplacementMatcher.
port 574f6fe127
(r37701)
original commit message:
Previously, the following schedule fragment:
1: Parameter[0](0)
2: Parameter[1](0)
7: Int32Constant[1]
8: Int32Sub(2, 7)
9: Load[kRepTagged|kTypeAny](1, 8)
would generate the following code (on ia32):
mov eax,[ebp+0x8]
mov ecx,[ebp+0xc]
sub eax,0x1
mov eax,[eax+ecx*1]
Now it generates:
mov eax,[ebp+0x8]
mov ecx,[ebp+0xc]
mov eax,[eax+ecx*1-1]
Similar pattern matching also now works on x64.
BUG=
Review-Url: https://codereview.chromium.org/2151753002
Cr-Commit-Position: refs/heads/master@{#37738}
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@ -86,12 +86,16 @@ class X87OperandGenerator final : public OperandGenerator {
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AddressingMode GenerateMemoryOperandInputs(Node* index, int scale, Node* base,
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Node* displacement_node,
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DisplacementMode displacement_mode,
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InstructionOperand inputs[],
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size_t* input_count) {
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AddressingMode mode = kMode_MRI;
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int32_t displacement = (displacement_node == nullptr)
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? 0
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: OpParameter<int32_t>(displacement_node);
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if (displacement_mode == kNegativeDisplacement) {
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displacement = -displacement;
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}
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if (base != nullptr) {
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if (base->opcode() == IrOpcode::kInt32Constant) {
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displacement += OpParameter<int32_t>(base);
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@ -149,8 +153,9 @@ class X87OperandGenerator final : public OperandGenerator {
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BaseWithIndexAndDisplacement32Matcher m(node, true);
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DCHECK(m.matches());
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if ((m.displacement() == nullptr || CanBeImmediate(m.displacement()))) {
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return GenerateMemoryOperandInputs(m.index(), m.scale(), m.base(),
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m.displacement(), inputs, input_count);
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return GenerateMemoryOperandInputs(
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m.index(), m.scale(), m.base(), m.displacement(),
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m.displacement_mode(), inputs, input_count);
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} else {
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inputs[(*input_count)++] = UseRegister(node->InputAt(0));
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inputs[(*input_count)++] = UseRegister(node->InputAt(1));
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@ -538,12 +543,14 @@ void VisitMod(InstructionSelector* selector, Node* node, ArchOpcode opcode) {
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}
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void EmitLea(InstructionSelector* selector, Node* result, Node* index,
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int scale, Node* base, Node* displacement) {
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int scale, Node* base, Node* displacement,
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DisplacementMode displacement_mode) {
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X87OperandGenerator g(selector);
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InstructionOperand inputs[4];
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size_t input_count = 0;
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AddressingMode mode = g.GenerateMemoryOperandInputs(
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index, scale, base, displacement, inputs, &input_count);
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AddressingMode mode =
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g.GenerateMemoryOperandInputs(index, scale, base, displacement,
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displacement_mode, inputs, &input_count);
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DCHECK_NE(0u, input_count);
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DCHECK_GE(arraysize(inputs), input_count);
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@ -564,7 +571,7 @@ void InstructionSelector::VisitWord32Shl(Node* node) {
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if (m.matches()) {
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Node* index = node->InputAt(0);
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Node* base = m.power_of_two_plus_one() ? index : nullptr;
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EmitLea(this, node, index, m.scale(), base, nullptr);
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EmitLea(this, node, index, m.scale(), base, nullptr, kPositiveDisplacement);
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return;
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}
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VisitShift(this, node, kX87Shl);
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@ -701,7 +708,8 @@ void InstructionSelector::VisitInt32Add(Node* node) {
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InstructionOperand inputs[4];
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size_t input_count = 0;
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AddressingMode mode = g.GenerateMemoryOperandInputs(
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m.index(), m.scale(), m.base(), m.displacement(), inputs, &input_count);
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m.index(), m.scale(), m.base(), m.displacement(), m.displacement_mode(),
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inputs, &input_count);
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DCHECK_NE(0u, input_count);
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DCHECK_GE(arraysize(inputs), input_count);
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@ -735,7 +743,7 @@ void InstructionSelector::VisitInt32Mul(Node* node) {
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if (m.matches()) {
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Node* index = node->InputAt(0);
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Node* base = m.power_of_two_plus_one() ? index : nullptr;
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EmitLea(this, node, index, m.scale(), base, nullptr);
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EmitLea(this, node, index, m.scale(), base, nullptr, kPositiveDisplacement);
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return;
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}
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X87OperandGenerator g(this);
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