AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

Create a macro list for X-sd instructions

Browse Source 
These are SSE2 instructions that deal with scalar double precision
values, and look like the packed double precision variant of the
instructions, but with a prefix.

E.g. sqrtpd is 66 0F 51, sqrtss is F2 0F 51.

We don't put this in the same list, even though the implementation
is very similar, because SSE2_INSTRUCTION_LIST is used in other
macros which generate AVX versions of this, and that overlaps with
another macro which generates AVX versions of these X-sd instructions.
I will tease this apart and clean it up in subsequent changes.

Bug: v8:9810
Change-Id: I0db64fe0d37df5685158331ce9f48bd1c763cc59
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1874510
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64688}
This commit is contained in:
Ng Zhi An 2019-10-30 12:45:10 -07:00 committed by Commit Bot
parent b8ac4eb4dc
commit a742d8fb2f
4 changed files with 12 additions and 158 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

128
src/codegen/x64/assembler-x64.cc
View File

@ -3392,114 +3392,6 @@ void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::addsd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x58);
emit_sse_operand(dst, src);
}
void Assembler::addsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x58);
emit_sse_operand(dst, src);
}
void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x59);
emit_sse_operand(dst, src);
}
void Assembler::mulsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x59);
emit_sse_operand(dst, src);
}
void Assembler::subsd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5C);
emit_sse_operand(dst, src);
}
void Assembler::subsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5C);
emit_sse_operand(dst, src);
}
void Assembler::divsd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5E);
emit_sse_operand(dst, src);
}
void Assembler::divsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5E);
emit_sse_operand(dst, src);
}
void Assembler::maxsd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5F);
emit_sse_operand(dst, src);
}
void Assembler::maxsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5F);
emit_sse_operand(dst, src);
}
void Assembler::minsd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5D);
emit_sse_operand(dst, src);
}
void Assembler::minsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5D);
emit_sse_operand(dst, src);
}
void Assembler::andpd(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0x66);
@ -3556,26 +3448,6 @@ void Assembler::xorpd(XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x51);
emit_sse_operand(dst, src);
}
void Assembler::sqrtsd(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x51);
emit_sse_operand(dst, src);
}
void Assembler::haddps(XMMRegister dst, XMMRegister src) {
DCHECK(IsEnabled(SSE3));
EnsureSpace ensure_space(this);

17
src/codegen/x64/assembler-x64.h
View File

@ -888,6 +888,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
// These SSE instructions have the same encoding as the SSE2 instructions.
SSE_INSTRUCTION_LIST_SS(DECLARE_SSE2_INSTRUCTION)
SSE2_INSTRUCTION_LIST(DECLARE_SSE2_INSTRUCTION)
SSE2_INSTRUCTION_LIST_SD(DECLARE_SSE2_INSTRUCTION)
#undef DECLARE_SSE2_INSTRUCTION
#define DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
@ -1053,28 +1054,12 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void cvtsd2si(Register dst, XMMRegister src);
void cvtsd2siq(Register dst, XMMRegister src);
void addsd(XMMRegister dst, XMMRegister src);
void addsd(XMMRegister dst, Operand src);
void subsd(XMMRegister dst, XMMRegister src);
void subsd(XMMRegister dst, Operand src);
void mulsd(XMMRegister dst, XMMRegister src);
void mulsd(XMMRegister dst, Operand src);
void divsd(XMMRegister dst, XMMRegister src);
void divsd(XMMRegister dst, Operand src);
void maxsd(XMMRegister dst, XMMRegister src);
void maxsd(XMMRegister dst, Operand src);
void minsd(XMMRegister dst, XMMRegister src);
void minsd(XMMRegister dst, Operand src);
void andpd(XMMRegister dst, XMMRegister src);
void andpd(XMMRegister dst, Operand src);
void orpd(XMMRegister dst, XMMRegister src);
void orpd(XMMRegister dst, Operand src);
void xorpd(XMMRegister dst, XMMRegister src);
void xorpd(XMMRegister dst, Operand src);
void sqrtsd(XMMRegister dst, XMMRegister src);
void sqrtsd(XMMRegister dst, Operand src);
void haddps(XMMRegister dst, XMMRegister src);
void haddps(XMMRegister dst, Operand src);

10
src/codegen/x64/sse-instr.h
View File

@ -88,6 +88,16 @@
V(por, 66, 0F, EB) \
V(pxor, 66, 0F, EF)
// Instructions dealing with scalar double-precision values.
#define SSE2_INSTRUCTION_LIST_SD(V) \
V(sqrtsd, F2, 0F, 51) \
V(addsd, F2, 0F, 58) \
V(mulsd, F2, 0F, 59) \
V(subsd, F2, 0F, 5C) \
V(minsd, F2, 0F, 5D) \
V(divsd, F2, 0F, 5E) \
V(maxsd, F2, 0F, 5F)
#define SSSE3_INSTRUCTION_LIST(V) \
V(pabsb, 66, 0F, 38, 1C) \
V(pabsw, 66, 0F, 38, 1D) \

15
test/cctest/test-disasm-x64.cc
View File

@ -425,20 +425,6 @@ TEST(DisasmX64) {
__ movdqa(xmm0, Operand(rbx, rcx, times_4, 10000));
__ movdqa(Operand(rbx, rcx, times_4, 10000), xmm0);
__ addsd(xmm1, xmm0);
__ addsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ mulsd(xmm1, xmm0);
__ mulsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ subsd(xmm1, xmm0);
__ subsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ divsd(xmm1, xmm0);
__ divsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ minsd(xmm1, xmm0);
__ minsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ maxsd(xmm1, xmm0);
__ maxsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ sqrtsd(xmm1, xmm0);
__ sqrtsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ ucomisd(xmm0, xmm1);
__ andpd(xmm0, xmm1);
@ -467,6 +453,7 @@ TEST(DisasmX64) {
__ instruction(xmm5, Operand(rdx, 4));
SSE2_INSTRUCTION_LIST(EMIT_SSE2_INSTR)
SSE2_INSTRUCTION_LIST_SD(EMIT_SSE2_INSTR)
#undef EMIT_SSE2_INSTR
}