Use VLDR instead of VMOVs from GPR when a 64-bit double can't be encoded as a VMOV immediate.
This requires constant blinding before it can be enabled. There are other interesting optimizations that can be added later, detailed in a TODO. BUG=optimization R=ulan@chromium.org,mstarzinger@chromium.org, hwennborg@google.com Review URL: https://chromiumcodereview.appspot.com/11191029 Patch from JF Bastien <jfb@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13286 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
ulan@chromium.org
parent
2e6a7c733b
commit
a7f9c491dc
@ -309,8 +309,11 @@ const Instr kPopRegPattern =
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// mov lr, pc
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const Instr kMovLrPc = al | MOV | kRegister_pc_Code | kRegister_lr_Code * B12;
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// ldr rd, [pc, #offset]
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const Instr kLdrPCMask = kCondMask | 15 * B24 | 7 * B20 | 15 * B16;
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const Instr kLdrPCPattern = al | 5 * B24 | L | kRegister_pc_Code * B16;
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const Instr kLdrPCMask = 15 * B24 | 7 * B20 | 15 * B16;
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const Instr kLdrPCPattern = 5 * B24 | L | kRegister_pc_Code * B16;
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// vldr dd, [pc, #offset]
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const Instr kVldrDPCMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8;
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const Instr kVldrDPCPattern = 13 * B24 | L | kRegister_pc_Code * B16 | 11 * B8;
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// blxcc rm
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const Instr kBlxRegMask =
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15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4;
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@ -351,6 +354,7 @@ Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
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positions_recorder_(this) {
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reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
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num_pending_reloc_info_ = 0;
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num_pending_64_bit_reloc_info_ = 0;
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next_buffer_check_ = 0;
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const_pool_blocked_nesting_ = 0;
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no_const_pool_before_ = 0;
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@ -369,6 +373,7 @@ void Assembler::GetCode(CodeDesc* desc) {
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// Emit constant pool if necessary.
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CheckConstPool(true, false);
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ASSERT(num_pending_reloc_info_ == 0);
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ASSERT(num_pending_64_bit_reloc_info_ == 0);
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// Set up code descriptor.
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desc->buffer = buffer_;
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@ -415,6 +420,11 @@ bool Assembler::IsLdrRegisterImmediate(Instr instr) {
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}
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bool Assembler::IsVldrDRegisterImmediate(Instr instr) {
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return (instr & (15 * B24 | 3 * B20 | 15 * B8)) == (13 * B24 | B20 | 11 * B8);
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}
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int Assembler::GetLdrRegisterImmediateOffset(Instr instr) {
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ASSERT(IsLdrRegisterImmediate(instr));
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bool positive = (instr & B23) == B23;
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@ -423,6 +433,15 @@ int Assembler::GetLdrRegisterImmediateOffset(Instr instr) {
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}
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int Assembler::GetVldrDRegisterImmediateOffset(Instr instr) {
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ASSERT(IsVldrDRegisterImmediate(instr));
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bool positive = (instr & B23) == B23;
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int offset = instr & kOff8Mask; // Zero extended offset.
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offset <<= 2;
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return positive ? offset : -offset;
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}
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Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) {
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ASSERT(IsLdrRegisterImmediate(instr));
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bool positive = offset >= 0;
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@ -435,6 +454,19 @@ Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) {
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}
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Instr Assembler::SetVldrDRegisterImmediateOffset(Instr instr, int offset) {
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ASSERT(IsVldrDRegisterImmediate(instr));
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ASSERT((offset & ~3) == offset); // Must be 64-bit aligned.
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bool positive = offset >= 0;
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if (!positive) offset = -offset;
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ASSERT(is_uint10(offset));
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// Set bit indicating whether the offset should be added.
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instr = (instr & ~B23) | (positive ? B23 : 0);
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// Set the actual offset. Its bottom 2 bits are zero.
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return (instr & ~kOff8Mask) | (offset >> 2);
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}
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bool Assembler::IsStrRegisterImmediate(Instr instr) {
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return (instr & (B27 | B26 | B25 | B22 | B20)) == B26;
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}
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@ -520,7 +552,14 @@ bool Assembler::IsLdrRegFpNegOffset(Instr instr) {
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bool Assembler::IsLdrPcImmediateOffset(Instr instr) {
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// Check the instruction is indeed a
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// ldr<cond> <Rd>, [pc +/- offset_12].
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return (instr & (kLdrPCMask & ~kCondMask)) == 0x051f0000;
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return (instr & kLdrPCMask) == kLdrPCPattern;
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}
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bool Assembler::IsVldrDPcImmediateOffset(Instr instr) {
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// Check the instruction is indeed a
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// vldr<cond> <Dd>, [pc +/- offset_10].
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return (instr & kVldrDPCMask) == kVldrDPCPattern;
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}
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@ -796,7 +835,7 @@ bool Operand::must_output_reloc_info(const Assembler* assembler) const {
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#endif // def DEBUG
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if (assembler != NULL && assembler->predictable_code_size()) return true;
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return Serializer::enabled();
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} else if (rmode_ == RelocInfo::NONE) {
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} else if (RelocInfo::IsNone(rmode_)) {
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return false;
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}
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return true;
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@ -2027,9 +2066,26 @@ void Assembler::vmov(const DwVfpRegister dst,
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if (CpuFeatures::IsSupported(VFP3) && FitsVMOVDoubleImmediate(imm, &enc)) {
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// The double can be encoded in the instruction.
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emit(cond | 0xE*B24 | 0xB*B20 | dst.code()*B12 | 0xB*B8 | enc);
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} else if (FLAG_enable_vldr_imm) {
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// TODO(jfb) Temporarily turned off until we have constant blinding or
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// some equivalent mitigation: an attacker can otherwise control
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// generated data which also happens to be executable, a Very Bad
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// Thing indeed.
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// Blinding gets tricky because we don't have xor, we probably
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// need to add/subtract without losing precision, which requires a
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// cookie value that Lithium is probably better positioned to
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// choose.
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// We could also add a few peepholes here like detecting 0.0 and
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// -0.0 and doing a vmov from the sequestered d14, forcing denorms
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// to zero (we set flush-to-zero), and normalizing NaN values.
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// We could also detect redundant values.
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// The code could also randomize the order of values, though
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// that's tricky because vldr has a limited reach. Furthermore
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// it breaks load locality.
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RecordRelocInfo(imm);
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vldr(dst, MemOperand(pc, 0), cond);
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} else {
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// Synthesise the double from ARM immediates. This could be implemented
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// using vldr from a constant pool.
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// Synthesise the double from ARM immediates.
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uint32_t lo, hi;
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DoubleAsTwoUInt32(imm, &lo, &hi);
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mov(ip, Operand(lo));
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@ -2592,6 +2648,7 @@ void Assembler::db(uint8_t data) {
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// to write pure data with no pointers and the constant pool should
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// be emitted before using db.
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ASSERT(num_pending_reloc_info_ == 0);
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ASSERT(num_pending_64_bit_reloc_info_ == 0);
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CheckBuffer();
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*reinterpret_cast<uint8_t*>(pc_) = data;
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pc_ += sizeof(uint8_t);
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@ -2603,6 +2660,7 @@ void Assembler::dd(uint32_t data) {
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// to write pure data with no pointers and the constant pool should
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// be emitted before using dd.
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ASSERT(num_pending_reloc_info_ == 0);
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ASSERT(num_pending_64_bit_reloc_info_ == 0);
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CheckBuffer();
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*reinterpret_cast<uint32_t*>(pc_) = data;
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pc_ += sizeof(uint32_t);
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@ -2626,16 +2684,9 @@ void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data,
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|| mode == DONT_USE_CONSTANT_POOL);
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// These modes do not need an entry in the constant pool.
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} else {
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ASSERT(num_pending_reloc_info_ < kMaxNumPendingRelocInfo);
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if (num_pending_reloc_info_ == 0) {
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first_const_pool_use_ = pc_offset();
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}
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pending_reloc_info_[num_pending_reloc_info_++] = rinfo;
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// Make sure the constant pool is not emitted in place of the next
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// instruction for which we just recorded relocation info.
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BlockConstPoolFor(1);
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RecordRelocInfoConstantPoolEntryHelper(rinfo);
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}
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if (rinfo.rmode() != RelocInfo::NONE) {
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if (!RelocInfo::IsNone(rinfo.rmode())) {
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// Don't record external references unless the heap will be serialized.
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if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
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#ifdef DEBUG
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@ -2661,14 +2712,38 @@ void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data,
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}
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}
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void Assembler::RecordRelocInfo(double data) {
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// We do not try to reuse pool constants.
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RelocInfo rinfo(pc_, data);
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RecordRelocInfoConstantPoolEntryHelper(rinfo);
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}
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void Assembler::RecordRelocInfoConstantPoolEntryHelper(const RelocInfo& rinfo) {
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ASSERT(num_pending_reloc_info_ < kMaxNumPendingRelocInfo);
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if (num_pending_reloc_info_ == 0) {
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first_const_pool_use_ = pc_offset();
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}
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pending_reloc_info_[num_pending_reloc_info_++] = rinfo;
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if (rinfo.rmode() == RelocInfo::NONE64) {
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++num_pending_64_bit_reloc_info_;
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}
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ASSERT(num_pending_64_bit_reloc_info_ <= num_pending_reloc_info_);
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// Make sure the constant pool is not emitted in place of the next
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// instruction for which we just recorded relocation info.
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BlockConstPoolFor(1);
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}
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void Assembler::BlockConstPoolFor(int instructions) {
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int pc_limit = pc_offset() + instructions * kInstrSize;
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if (no_const_pool_before_ < pc_limit) {
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// If there are some pending entries, the constant pool cannot be blocked
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// further than first_const_pool_use_ + kMaxDistToPool
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// further than constant pool instruction's reach.
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ASSERT((num_pending_reloc_info_ == 0) ||
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(pc_limit < (first_const_pool_use_ + kMaxDistToPool)));
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(pc_limit - first_const_pool_use_ < kMaxDistToIntPool));
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// TODO(jfb) Also check 64-bit entries are in range (requires splitting
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// them up from 32-bit entries).
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no_const_pool_before_ = pc_limit;
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}
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@ -2690,29 +2765,60 @@ void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
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// There is nothing to do if there are no pending constant pool entries.
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if (num_pending_reloc_info_ == 0) {
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ASSERT(num_pending_64_bit_reloc_info_ == 0);
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// Calculate the offset of the next check.
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next_buffer_check_ = pc_offset() + kCheckPoolInterval;
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return;
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}
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// We emit a constant pool when:
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// * requested to do so by parameter force_emit (e.g. after each function).
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// * the distance to the first instruction accessing the constant pool is
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// kAvgDistToPool or more.
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// * no jump is required and the distance to the first instruction accessing
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// the constant pool is at least kMaxDistToPool / 2.
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ASSERT(first_const_pool_use_ >= 0);
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int dist = pc_offset() - first_const_pool_use_;
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if (!force_emit && dist < kAvgDistToPool &&
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(require_jump || (dist < (kMaxDistToPool / 2)))) {
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return;
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}
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// Check that the code buffer is large enough before emitting the constant
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// pool (include the jump over the pool and the constant pool marker and
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// the gap to the relocation information).
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// Note 64-bit values are wider, and the first one needs to be 64-bit aligned.
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int jump_instr = require_jump ? kInstrSize : 0;
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int size = jump_instr + kInstrSize + num_pending_reloc_info_ * kPointerSize;
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int size_up_to_marker = jump_instr + kInstrSize;
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int size_after_marker = num_pending_reloc_info_ * kPointerSize;
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bool has_fp_values = (num_pending_64_bit_reloc_info_ > 0);
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// 64-bit values must be 64-bit aligned.
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// We'll start emitting at PC: branch+marker, then 32-bit values, then
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// 64-bit values which might need to be aligned.
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bool require_64_bit_align = has_fp_values &&
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(((uintptr_t)pc_ + size_up_to_marker + size_after_marker) & 0x3);
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if (require_64_bit_align) {
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size_after_marker += kInstrSize;
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}
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// num_pending_reloc_info_ also contains 64-bit entries, the above code
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// therefore already counted half of the size for 64-bit entries. Add the
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// remaining size.
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STATIC_ASSERT(kPointerSize == kDoubleSize / 2);
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size_after_marker += num_pending_64_bit_reloc_info_ * (kDoubleSize / 2);
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int size = size_up_to_marker + size_after_marker;
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// We emit a constant pool when:
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// * requested to do so by parameter force_emit (e.g. after each function).
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// * the distance from the first instruction accessing the constant pool to
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// any of the constant pool entries will exceed its limit the next
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// time the pool is checked. This is overly restrictive, but we don't emit
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// constant pool entries in-order so it's conservatively correct.
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// * the instruction doesn't require a jump after itself to jump over the
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// constant pool, and we're getting close to running out of range.
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if (!force_emit) {
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ASSERT((first_const_pool_use_ >= 0) && (num_pending_reloc_info_ > 0));
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int dist = pc_offset() + size - first_const_pool_use_;
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if (has_fp_values) {
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if ((dist < kMaxDistToFPPool - kCheckPoolInterval) &&
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(require_jump || (dist < kMaxDistToFPPool / 2))) {
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return;
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}
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} else {
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if ((dist < kMaxDistToIntPool - kCheckPoolInterval) &&
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(require_jump || (dist < kMaxDistToIntPool / 2))) {
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return;
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}
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}
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}
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int needed_space = size + kGap;
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while (buffer_space() <= needed_space) GrowBuffer();
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@ -2729,10 +2835,43 @@ void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
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}
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// Put down constant pool marker "Undefined instruction".
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emit(kConstantPoolMarker |
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EncodeConstantPoolLength(num_pending_reloc_info_));
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// The data size helps disassembly know what to print.
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emit(kConstantPoolMarker | EncodeConstantPoolLength(size_after_marker));
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// Emit constant pool entries.
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if (require_64_bit_align) {
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emit(kConstantPoolMarker);
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}
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// Emit 64-bit constant pool entries first: their range is smaller than
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// 32-bit entries.
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for (int i = 0; i < num_pending_reloc_info_; i++) {
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RelocInfo& rinfo = pending_reloc_info_[i];
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if (rinfo.rmode() != RelocInfo::NONE64) {
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// 32-bit values emitted later.
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continue;
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}
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ASSERT(!((uintptr_t)pc_ & 0x3)); // Check 64-bit alignment.
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Instr instr = instr_at(rinfo.pc());
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// Instruction to patch must be 'vldr rd, [pc, #offset]' with offset == 0.
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ASSERT((IsVldrDPcImmediateOffset(instr) &&
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GetVldrDRegisterImmediateOffset(instr) == 0));
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int delta = pc_ - rinfo.pc() - kPcLoadDelta;
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ASSERT(is_uint10(delta));
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instr_at_put(rinfo.pc(), SetVldrDRegisterImmediateOffset(instr, delta));
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const double double_data = rinfo.data64();
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uint64_t uint_data = 0;
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memcpy(&uint_data, &double_data, sizeof(double_data));
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emit(uint_data & 0xFFFFFFFF);
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emit(uint_data >> 32);
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}
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// Emit 32-bit constant pool entries.
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for (int i = 0; i < num_pending_reloc_info_; i++) {
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RelocInfo& rinfo = pending_reloc_info_[i];
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ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
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@ -2740,25 +2879,35 @@ void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
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rinfo.rmode() != RelocInfo::STATEMENT_POSITION &&
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rinfo.rmode() != RelocInfo::CONST_POOL);
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if (rinfo.rmode() == RelocInfo::NONE64) {
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// 64-bit values emitted earlier.
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continue;
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}
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Instr instr = instr_at(rinfo.pc());
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// Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
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// 64-bit loads shouldn't get here.
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ASSERT(!IsVldrDPcImmediateOffset(instr));
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int delta = pc_ - rinfo.pc() - kPcLoadDelta;
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// 0 is the smallest delta:
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// ldr rd, [pc, #0]
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// constant pool marker
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// data
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if (IsLdrPcImmediateOffset(instr) &&
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GetLdrRegisterImmediateOffset(instr) == 0) {
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int delta = pc_ - rinfo.pc() - kPcLoadDelta;
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// 0 is the smallest delta:
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// ldr rd, [pc, #0]
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// constant pool marker
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// data
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ASSERT(is_uint12(delta));
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instr_at_put(rinfo.pc(), SetLdrRegisterImmediateOffset(instr, delta));
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emit(rinfo.data());
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} else {
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ASSERT(IsMovW(instr));
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emit(rinfo.data());
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}
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emit(rinfo.data());
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}
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num_pending_reloc_info_ = 0;
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num_pending_64_bit_reloc_info_ = 0;
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first_const_pool_use_ = -1;
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RecordComment("]");
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@ -1278,8 +1278,11 @@ class Assembler : public AssemblerBase {
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static bool IsBranch(Instr instr);
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static int GetBranchOffset(Instr instr);
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static bool IsLdrRegisterImmediate(Instr instr);
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static bool IsVldrDRegisterImmediate(Instr instr);
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static int GetLdrRegisterImmediateOffset(Instr instr);
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static int GetVldrDRegisterImmediateOffset(Instr instr);
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static Instr SetLdrRegisterImmediateOffset(Instr instr, int offset);
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static Instr SetVldrDRegisterImmediateOffset(Instr instr, int offset);
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static bool IsStrRegisterImmediate(Instr instr);
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static Instr SetStrRegisterImmediateOffset(Instr instr, int offset);
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static bool IsAddRegisterImmediate(Instr instr);
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@ -1294,6 +1297,7 @@ class Assembler : public AssemblerBase {
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static bool IsStrRegFpNegOffset(Instr instr);
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static bool IsLdrRegFpNegOffset(Instr instr);
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static bool IsLdrPcImmediateOffset(Instr instr);
|
||||
static bool IsVldrDPcImmediateOffset(Instr instr);
|
||||
static bool IsTstImmediate(Instr instr);
|
||||
static bool IsCmpRegister(Instr instr);
|
||||
static bool IsCmpImmediate(Instr instr);
|
||||
@ -1304,12 +1308,13 @@ class Assembler : public AssemblerBase {
|
||||
static bool IsMovW(Instr instr);
|
||||
|
||||
// Constants in pools are accessed via pc relative addressing, which can
|
||||
// reach +/-4KB thereby defining a maximum distance between the instruction
|
||||
// and the accessed constant.
|
||||
static const int kMaxDistToPool = 4*KB;
|
||||
static const int kMaxNumPendingRelocInfo = kMaxDistToPool/kInstrSize;
|
||||
STATIC_ASSERT((kConstantPoolLengthMaxMask & kMaxNumPendingRelocInfo) ==
|
||||
kMaxNumPendingRelocInfo);
|
||||
// reach +/-4KB for integer PC-relative loads and +/-1KB for floating-point
|
||||
// PC-relative loads, thereby defining a maximum distance between the
|
||||
// instruction and the accessed constant.
|
||||
static const int kMaxDistToIntPool = 4*KB;
|
||||
static const int kMaxDistToFPPool = 1*KB;
|
||||
// All relocations could be integer, it therefore acts as the limit.
|
||||
static const int kMaxNumPendingRelocInfo = kMaxDistToIntPool/kInstrSize;
|
||||
|
||||
// Postpone the generation of the constant pool for the specified number of
|
||||
// instructions.
|
||||
@ -1349,7 +1354,9 @@ class Assembler : public AssemblerBase {
|
||||
if (--const_pool_blocked_nesting_ == 0) {
|
||||
// Check the constant pool hasn't been blocked for too long.
|
||||
ASSERT((num_pending_reloc_info_ == 0) ||
|
||||
(pc_offset() < (first_const_pool_use_ + kMaxDistToPool)));
|
||||
(pc_offset() < (first_const_pool_use_ + kMaxDistToIntPool)));
|
||||
ASSERT((num_pending_64_bit_reloc_info_ == 0) ||
|
||||
(pc_offset() < (first_const_pool_use_ + kMaxDistToFPPool)));
|
||||
// Two cases:
|
||||
// * no_const_pool_before_ >= next_buffer_check_ and the emission is
|
||||
// still blocked
|
||||
@ -1392,13 +1399,6 @@ class Assembler : public AssemblerBase {
|
||||
static const int kCheckPoolInterval = kCheckPoolIntervalInst * kInstrSize;
|
||||
|
||||
|
||||
// Average distance beetween a constant pool and the first instruction
|
||||
// accessing the constant pool. Longer distance should result in less I-cache
|
||||
// pollution.
|
||||
// In practice the distance will be smaller since constant pool emission is
|
||||
// forced after function return and sometimes after unconditional branches.
|
||||
static const int kAvgDistToPool = kMaxDistToPool - kCheckPoolInterval;
|
||||
|
||||
// Emission of the constant pool may be blocked in some code sequences.
|
||||
int const_pool_blocked_nesting_; // Block emission if this is not zero.
|
||||
int no_const_pool_before_; // Block emission before this pc offset.
|
||||
@ -1423,6 +1423,9 @@ class Assembler : public AssemblerBase {
|
||||
RelocInfo pending_reloc_info_[kMaxNumPendingRelocInfo];
|
||||
// number of pending reloc info entries in the buffer
|
||||
int num_pending_reloc_info_;
|
||||
// Number of pending reloc info entries included above which also happen to
|
||||
// be 64-bit.
|
||||
int num_pending_64_bit_reloc_info_;
|
||||
|
||||
// The bound position, before this we cannot do instruction elimination.
|
||||
int last_bound_pos_;
|
||||
@ -1459,6 +1462,8 @@ class Assembler : public AssemblerBase {
|
||||
// Record reloc info for current pc_
|
||||
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0,
|
||||
UseConstantPoolMode mode = USE_CONSTANT_POOL);
|
||||
void RecordRelocInfo(double data);
|
||||
void RecordRelocInfoConstantPoolEntryHelper(const RelocInfo& rinfo);
|
||||
|
||||
friend class RegExpMacroAssemblerARM;
|
||||
friend class RelocInfo;
|
||||
|
||||
@ -267,7 +267,8 @@ enum {
|
||||
kCoprocessorMask = 15 << 8,
|
||||
kOpCodeMask = 15 << 21, // In data-processing instructions.
|
||||
kImm24Mask = (1 << 24) - 1,
|
||||
kOff12Mask = (1 << 12) - 1
|
||||
kOff12Mask = (1 << 12) - 1,
|
||||
kOff8Mask = (1 << 8) - 1
|
||||
};
|
||||
|
||||
|
||||
@ -464,6 +465,9 @@ extern const Instr kMovLrPc;
|
||||
// ldr rd, [pc, #offset]
|
||||
extern const Instr kLdrPCMask;
|
||||
extern const Instr kLdrPCPattern;
|
||||
// vldr dd, [pc, #offset]
|
||||
extern const Instr kVldrDPCMask;
|
||||
extern const Instr kVldrDPCPattern;
|
||||
// blxcc rm
|
||||
extern const Instr kBlxRegMask;
|
||||
|
||||
|
||||
@ -693,7 +693,9 @@ RelocIterator::RelocIterator(const CodeDesc& desc, int mode_mask) {
|
||||
const char* RelocInfo::RelocModeName(RelocInfo::Mode rmode) {
|
||||
switch (rmode) {
|
||||
case RelocInfo::NONE:
|
||||
return "no reloc";
|
||||
return "no reloc 32";
|
||||
case RelocInfo::NONE64:
|
||||
return "no reloc 64";
|
||||
case RelocInfo::EMBEDDED_OBJECT:
|
||||
return "embedded object";
|
||||
case RelocInfo::CONSTRUCT_CALL:
|
||||
@ -817,6 +819,7 @@ void RelocInfo::Verify() {
|
||||
case CONST_POOL:
|
||||
case DEBUG_BREAK_SLOT:
|
||||
case NONE:
|
||||
case NONE64:
|
||||
break;
|
||||
case NUMBER_OF_MODES:
|
||||
UNREACHABLE();
|
||||
|
||||
@ -248,7 +248,8 @@ class RelocInfo BASE_EMBEDDED {
|
||||
// add more as needed
|
||||
// Pseudo-types
|
||||
NUMBER_OF_MODES, // There are at most 15 modes with noncompact encoding.
|
||||
NONE, // never recorded
|
||||
NONE, // never recorded 32-bit value
|
||||
NONE64, // never recorded 64-bit value
|
||||
CODE_AGE_SEQUENCE, // Not stored in RelocInfo array, used explictly by
|
||||
// code aging.
|
||||
FIRST_REAL_RELOC_MODE = CODE_TARGET,
|
||||
@ -268,6 +269,9 @@ class RelocInfo BASE_EMBEDDED {
|
||||
RelocInfo(byte* pc, Mode rmode, intptr_t data, Code* host)
|
||||
: pc_(pc), rmode_(rmode), data_(data), host_(host) {
|
||||
}
|
||||
RelocInfo(byte* pc, double data64)
|
||||
: pc_(pc), rmode_(NONE64), data64_(data64), host_(NULL) {
|
||||
}
|
||||
|
||||
static inline bool IsRealRelocMode(Mode mode) {
|
||||
return mode >= FIRST_REAL_RELOC_MODE &&
|
||||
@ -315,6 +319,9 @@ class RelocInfo BASE_EMBEDDED {
|
||||
static inline bool IsDebugBreakSlot(Mode mode) {
|
||||
return mode == DEBUG_BREAK_SLOT;
|
||||
}
|
||||
static inline bool IsNone(Mode mode) {
|
||||
return mode == NONE || mode == NONE64;
|
||||
}
|
||||
static inline bool IsCodeAgeSequence(Mode mode) {
|
||||
return mode == CODE_AGE_SEQUENCE;
|
||||
}
|
||||
@ -325,6 +332,7 @@ class RelocInfo BASE_EMBEDDED {
|
||||
void set_pc(byte* pc) { pc_ = pc; }
|
||||
Mode rmode() const { return rmode_; }
|
||||
intptr_t data() const { return data_; }
|
||||
double data64() const { return data64_; }
|
||||
Code* host() const { return host_; }
|
||||
|
||||
// Apply a relocation by delta bytes
|
||||
@ -423,7 +431,10 @@ class RelocInfo BASE_EMBEDDED {
|
||||
// comment).
|
||||
byte* pc_;
|
||||
Mode rmode_;
|
||||
intptr_t data_;
|
||||
union {
|
||||
intptr_t data_;
|
||||
double data64_;
|
||||
};
|
||||
Code* host_;
|
||||
// Code and Embedded Object pointers on some platforms are stored split
|
||||
// across two consecutive 32-bit instructions. Heap management
|
||||
|
||||
@ -300,6 +300,8 @@ DEFINE_bool(enable_unaligned_accesses, true,
|
||||
"enable unaligned accesses for ARMv7 (ARM only)")
|
||||
DEFINE_bool(enable_fpu, true,
|
||||
"enable use of MIPS FPU instructions if available (MIPS only)")
|
||||
DEFINE_bool(enable_vldr_imm, false,
|
||||
"enable use of constant pools for double immediate (ARM only)")
|
||||
|
||||
// bootstrapper.cc
|
||||
DEFINE_string(expose_natives_as, NULL, "expose natives in global object")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user