Simulate and disasm NOP on ARM
R=ulan@chromium.org Review URL: https://chromiumcodereview.appspot.com/11116011 Patch from JF Bastien <jfb@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12737 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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@ -2440,15 +2440,19 @@ void Assembler::vsqrt(const DwVfpRegister dst,
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// Pseudo instructions.
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void Assembler::nop(int type) {
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// This is mov rx, rx.
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ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop.
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// ARMv6{K/T2} and v7 have an actual NOP instruction but it serializes
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// some of the CPU's pipeline and has to issue. Older ARM chips simply used
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// MOV Rx, Rx as NOP and it performs better even in newer CPUs.
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// We therefore use MOV Rx, Rx, even on newer CPUs, and use Rx to encode
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// a type.
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ASSERT(0 <= type && type <= 14); // mov pc, pc isn't a nop.
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emit(al | 13*B21 | type*B12 | type);
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}
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bool Assembler::IsNop(Instr instr, int type) {
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ASSERT(0 <= type && type <= 14); // mov pc, pc isn't a nop.
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// Check for mov rx, rx where x = type.
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ASSERT(0 <= type && type <= 14); // mov pc, pc is not a nop.
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return instr == (al | 13*B21 | type*B12 | type);
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}
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@ -687,6 +687,9 @@ class Instruction {
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&& (Bit(20) == 0)
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&& ((Bit(7) == 0)); }
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// Test for a nop instruction, which falls under type 1.
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inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; }
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// Test for a stop instruction.
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inline bool IsStop() const {
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return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode);
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@ -830,6 +830,8 @@ void Decoder::DecodeType01(Instruction* instr) {
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} else {
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Unknown(instr); // not used by V8
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}
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} else if ((type == 1) && instr->IsNopType1()) {
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Format(instr, "nop'cond");
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} else {
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switch (instr->OpcodeField()) {
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case AND: {
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@ -2183,6 +2183,8 @@ void Simulator::DecodeType01(Instruction* instr) {
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PrintF("%08x\n", instr->InstructionBits());
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UNIMPLEMENTED();
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}
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} else if ((type == 1) && instr->IsNopType1()) {
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// NOP.
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} else {
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int rd = instr->RdValue();
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int rn = instr->RnValue();
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