AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

[riscv64] Optimize RiscvCmpzero emit extra instruction

Browse Source 
Bug: v8:12151

Change-Id: I97d15e9089164c05715b3121839d4bd6ba08cb70
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131782
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#76594}
This commit is contained in:
Lu Yahan 2021-08-31 11:25:29 +08:00 committed by V8 LUCI CQ
parent 1c381f9a83
commit a9062f882f
2 changed files with 26 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/compiler/backend/riscv64/code-generator-riscv64.cc
View File

@ -1882,6 +1882,19 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
<< "\""; \
UNIMPLEMENTED();
bool IsInludeEqual(Condition cc) {
switch (cc) {
case equal:
case greater_equal:
case less_equal:
case Uless_equal:
case Ugreater_equal:
return true;
default:
return false;
}
}
void AssembleBranchToLabels(CodeGenerator* gen, TurboAssembler* tasm,
Instruction* instr, FlagsCondition condition,
Label* tlabel, Label* flabel, bool fallthru) {
@ -1936,7 +1949,11 @@ void AssembleBranchToLabels(CodeGenerator* gen, TurboAssembler* tasm,
__ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1));
} else if (instr->arch_opcode() == kRiscvCmpZero) {
cc = FlagsConditionToConditionCmp(condition);
__ Branch(tlabel, cc, i.InputRegister(0), Operand(zero_reg));
if (i.InputOrZeroRegister(0) == zero_reg && IsInludeEqual(cc)) {
__ Branch(tlabel);
} else {
__ Branch(tlabel, cc, i.InputRegister(0), Operand(zero_reg));
}
} else if (instr->arch_opcode() == kArchStackPointerGreaterThan) {
cc = FlagsConditionToConditionCmp(condition);
Register lhs_register = sp;

12
src/compiler/backend/riscv64/instruction-selector-riscv64.cc
View File

@ -1782,7 +1782,8 @@ void VisitWordCompare(InstructionSelector* selector, Node* node,
Int32BinopMatcher m(node, true);
NumberBinopMatcher n(node, true);
if (m.right().Is(0) || n.right().IsZero()) {
VisitWordCompareZero(selector, g.UseRegister(left), cont);
VisitWordCompareZero(selector, g.UseRegisterOrImmediateZero(left),
cont);
} else {
VisitCompare(selector, opcode, g.UseRegister(left),
g.UseRegister(right), cont);
@ -1795,7 +1796,8 @@ void VisitWordCompare(InstructionSelector* selector, Node* node,
case kUnsignedGreaterThanOrEqual: {
Int32BinopMatcher m(node, true);
if (m.right().Is(0)) {
VisitWordCompareZero(selector, g.UseRegister(left), cont);
VisitWordCompareZero(selector, g.UseRegisterOrImmediateZero(left),
cont);
} else {
VisitCompare(selector, opcode, g.UseRegister(left),
g.UseImmediate(right), cont);
@ -1804,7 +1806,8 @@ void VisitWordCompare(InstructionSelector* selector, Node* node,
default:
Int32BinopMatcher m(node, true);
if (m.right().Is(0)) {
VisitWordCompareZero(selector, g.UseRegister(left), cont);
VisitWordCompareZero(selector, g.UseRegisterOrImmediateZero(left),
cont);
} else {
VisitCompare(selector, opcode, g.UseRegister(left),
g.UseRegister(right), cont);
@ -1926,7 +1929,8 @@ void VisitWord64Compare(InstructionSelector* selector, Node* node,
void EmitWordCompareZero(InstructionSelector* selector, Node* value,
FlagsContinuation* cont) {
RiscvOperandGenerator g(selector);
selector->EmitWithContinuation(kRiscvCmpZero, g.UseRegister(value), cont);
selector->EmitWithContinuation(kRiscvCmpZero,
g.UseRegisterOrImmediateZero(value), cont);
}
void VisitAtomicLoad(InstructionSelector* selector, Node* node,