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VectorICs: vector [keyed]store ic MISS handling infrastructure.

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BUG=

Review URL: https://codereview.chromium.org/1255883002

Cr-Commit-Position: refs/heads/master@{#29870}
This commit is contained in:
mvstanton 2015-07-27 05:49:58 -07:00 committed by Commit bot
parent 48e38e569c
commit a913f4bf5c
10 changed files with 173 additions and 68 deletions
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52
src/arm/macro-assembler-arm.h
View File

@ -325,9 +325,7 @@ class MacroAssembler: public Assembler {
// Push three registers. Pushes leftmost register first (to highest address).
void Push(Register src1, Register src2, Register src3, Condition cond = al) {
DCHECK(!src1.is(src2));
DCHECK(!src2.is(src3));
DCHECK(!src1.is(src3));
DCHECK(!AreAliased(src1, src2, src3));
if (src1.code() > src2.code()) {
if (src2.code() > src3.code()) {
stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
@ -347,12 +345,7 @@ class MacroAssembler: public Assembler {
Register src3,
Register src4,
Condition cond = al) {
DCHECK(!src1.is(src2));
DCHECK(!src2.is(src3));
DCHECK(!src1.is(src3));
DCHECK(!src1.is(src4));
DCHECK(!src2.is(src4));
DCHECK(!src3.is(src4));
DCHECK(!AreAliased(src1, src2, src3, src4));
if (src1.code() > src2.code()) {
if (src2.code() > src3.code()) {
if (src3.code() > src4.code()) {
@ -374,6 +367,36 @@ class MacroAssembler: public Assembler {
}
}
// Push five registers. Pushes leftmost register first (to highest address).
void Push(Register src1, Register src2, Register src3, Register src4,
Register src5, Condition cond = al) {
DCHECK(!AreAliased(src1, src2, src3, src4, src5));
if (src1.code() > src2.code()) {
if (src2.code() > src3.code()) {
if (src3.code() > src4.code()) {
if (src4.code() > src5.code()) {
stm(db_w, sp,
src1.bit() | src2.bit() | src3.bit() | src4.bit() | src5.bit(),
cond);
} else {
stm(db_w, sp, src1.bit() | src2.bit() | src3.bit() | src4.bit(),
cond);
str(src5, MemOperand(sp, 4, NegPreIndex), cond);
}
} else {
stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
Push(src4, src5, cond);
}
} else {
stm(db_w, sp, src1.bit() | src2.bit(), cond);
Push(src3, src4, src5, cond);
}
} else {
str(src1, MemOperand(sp, 4, NegPreIndex), cond);
Push(src2, src3, src4, src5, cond);
}
}
// Pop two registers. Pops rightmost register first (from lower address).
void Pop(Register src1, Register src2, Condition cond = al) {
DCHECK(!src1.is(src2));
@ -387,9 +410,7 @@ class MacroAssembler: public Assembler {
// Pop three registers. Pops rightmost register first (from lower address).
void Pop(Register src1, Register src2, Register src3, Condition cond = al) {
DCHECK(!src1.is(src2));
DCHECK(!src2.is(src3));
DCHECK(!src1.is(src3));
DCHECK(!AreAliased(src1, src2, src3));
if (src1.code() > src2.code()) {
if (src2.code() > src3.code()) {
ldm(ia_w, sp, src1.bit() | src2.bit() | src3.bit(), cond);
@ -409,12 +430,7 @@ class MacroAssembler: public Assembler {
Register src3,
Register src4,
Condition cond = al) {
DCHECK(!src1.is(src2));
DCHECK(!src2.is(src3));
DCHECK(!src1.is(src3));
DCHECK(!src1.is(src4));
DCHECK(!src2.is(src4));
DCHECK(!src3.is(src4));
DCHECK(!AreAliased(src1, src2, src3, src4));
if (src1.code() > src2.code()) {
if (src2.code() > src3.code()) {
if (src3.code() > src4.code()) {

28
src/ic/arm/ic-arm.cc
View File

@ -464,12 +464,24 @@ void KeyedLoadIC::GenerateMegamorphic(MacroAssembler* masm,
}
void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
// Push receiver, key and value for runtime call.
__ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
StoreDescriptor::ValueRegister());
static void StoreIC_PushArgs(MacroAssembler* masm) {
if (FLAG_vector_stores) {
__ Push(StoreDescriptor::ReceiverRegister(),
StoreDescriptor::NameRegister(), StoreDescriptor::ValueRegister(),
VectorStoreICDescriptor::SlotRegister(),
VectorStoreICDescriptor::VectorRegister());
} else {
__ Push(StoreDescriptor::ReceiverRegister(),
StoreDescriptor::NameRegister(), StoreDescriptor::ValueRegister());
}
}
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, 3, 1);
void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
StoreIC_PushArgs(masm);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, args, 1);
}
@ -767,11 +779,11 @@ void StoreIC::GenerateMegamorphic(MacroAssembler* masm) {
void StoreIC::GenerateMiss(MacroAssembler* masm) {
__ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
StoreDescriptor::ValueRegister());
StoreIC_PushArgs(masm);
// Perform tail call to the entry.
__ TailCallRuntime(Runtime::kStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1);
}

27
src/ic/arm64/ic-arm64.cc
View File

@ -471,14 +471,25 @@ void KeyedLoadIC::GenerateMegamorphic(MacroAssembler* masm,
}
static void StoreIC_PushArgs(MacroAssembler* masm) {
if (FLAG_vector_stores) {
__ Push(StoreDescriptor::ReceiverRegister(),
StoreDescriptor::NameRegister(), StoreDescriptor::ValueRegister(),
VectorStoreICDescriptor::SlotRegister(),
VectorStoreICDescriptor::VectorRegister());
} else {
__ Push(StoreDescriptor::ReceiverRegister(),
StoreDescriptor::NameRegister(), StoreDescriptor::ValueRegister());
}
}
void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
ASM_LOCATION("KeyedStoreIC::GenerateMiss");
StoreIC_PushArgs(masm);
// Push receiver, key and value for runtime call.
__ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
StoreDescriptor::ValueRegister());
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, args, 1);
}
@ -765,11 +776,11 @@ void StoreIC::GenerateMegamorphic(MacroAssembler* masm) {
void StoreIC::GenerateMiss(MacroAssembler* masm) {
__ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
StoreDescriptor::ValueRegister());
StoreIC_PushArgs(masm);
// Tail call to the entry.
__ TailCallRuntime(Runtime::kStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1);
}

29
src/ic/ia32/ic-ia32.cc
View File

@ -751,13 +751,24 @@ static void StoreIC_PushArgs(MacroAssembler* masm) {
Register name = StoreDescriptor::NameRegister();
Register value = StoreDescriptor::ValueRegister();
DCHECK(!ebx.is(receiver) && !ebx.is(name) && !ebx.is(value));
if (FLAG_vector_stores) {
Register slot = VectorStoreICDescriptor::SlotRegister();
Register vector = VectorStoreICDescriptor::VectorRegister();
__ pop(ebx);
__ push(receiver);
__ push(name);
__ push(value);
__ push(ebx);
__ xchg(receiver, Operand(esp, 0));
__ push(name);
__ push(value);
__ push(slot);
__ push(vector);
__ push(receiver); // Contains the return address.
} else {
DCHECK(!ebx.is(receiver) && !ebx.is(name) && !ebx.is(value));
__ pop(ebx);
__ push(receiver);
__ push(name);
__ push(value);
__ push(ebx);
}
}
@ -766,7 +777,8 @@ void StoreIC::GenerateMiss(MacroAssembler* masm) {
StoreIC_PushArgs(masm);
// Perform tail call to the entry.
__ TailCallRuntime(Runtime::kStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1);
}
@ -802,7 +814,8 @@ void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
StoreIC_PushArgs(masm);
// Do tail-call to runtime routine.
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, args, 1);
}

4
src/ic/ic.cc
View File

@ -2478,10 +2478,6 @@ RUNTIME_FUNCTION(Runtime_StoreIC_MissFromStubFailure) {
Handle<Object> value = args.at<Object>(2);
Handle<Object> result;
// Bailouts from transitioning stores may have the map to transition to as an
// extra argument.
DCHECK(args.length() < 4 || args.at<Object>(3)->IsMap());
if (FLAG_vector_stores) {
DCHECK(args.length() == 5 || args.length() == 6);
Handle<Smi> slot = args.at<Smi>(3);

29
src/ic/mips/ic-mips.cc
View File

@ -742,12 +742,24 @@ void KeyedStoreIC::GenerateMegamorphic(MacroAssembler* masm,
}
void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
// Push receiver, key and value for runtime call.
__ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
StoreDescriptor::ValueRegister());
static void StoreIC_PushArgs(MacroAssembler* masm) {
if (FLAG_vector_stores) {
__ Push(StoreDescriptor::ReceiverRegister(),
StoreDescriptor::NameRegister(), StoreDescriptor::ValueRegister(),
VectorStoreICDescriptor::SlotRegister(),
VectorStoreICDescriptor::VectorRegister());
} else {
__ Push(StoreDescriptor::ReceiverRegister(),
StoreDescriptor::NameRegister(), StoreDescriptor::ValueRegister());
}
}
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, 3, 1);
void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
StoreIC_PushArgs(masm);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, args, 1);
}
@ -770,10 +782,11 @@ void StoreIC::GenerateMegamorphic(MacroAssembler* masm) {
void StoreIC::GenerateMiss(MacroAssembler* masm) {
__ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
StoreDescriptor::ValueRegister());
StoreIC_PushArgs(masm);
// Perform tail call to the entry.
__ TailCallRuntime(Runtime::kStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1);
}

29
src/ic/mips64/ic-mips64.cc
View File

@ -740,12 +740,24 @@ void KeyedStoreIC::GenerateMegamorphic(MacroAssembler* masm,
}
void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
// Push receiver, key and value for runtime call.
__ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
StoreDescriptor::ValueRegister());
static void StoreIC_PushArgs(MacroAssembler* masm) {
if (FLAG_vector_stores) {
__ Push(StoreDescriptor::ReceiverRegister(),
StoreDescriptor::NameRegister(), StoreDescriptor::ValueRegister(),
VectorStoreICDescriptor::SlotRegister(),
VectorStoreICDescriptor::VectorRegister());
} else {
__ Push(StoreDescriptor::ReceiverRegister(),
StoreDescriptor::NameRegister(), StoreDescriptor::ValueRegister());
}
}
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, 3, 1);
void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
StoreIC_PushArgs(masm);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, args, 1);
}
@ -768,10 +780,11 @@ void StoreIC::GenerateMegamorphic(MacroAssembler* masm) {
void StoreIC::GenerateMiss(MacroAssembler* masm) {
__ Push(StoreDescriptor::ReceiverRegister(), StoreDescriptor::NameRegister(),
StoreDescriptor::ValueRegister());
StoreIC_PushArgs(masm);
// Perform tail call to the entry.
__ TailCallRuntime(Runtime::kStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1);
}

21
src/ic/x64/ic-x64.cc
View File

@ -753,14 +753,21 @@ static void StoreIC_PushArgs(MacroAssembler* masm) {
Register receiver = StoreDescriptor::ReceiverRegister();
Register name = StoreDescriptor::NameRegister();
Register value = StoreDescriptor::ValueRegister();
Register temp = r11;
DCHECK(!temp.is(receiver) && !temp.is(name) && !temp.is(value));
DCHECK(!rbx.is(receiver) && !rbx.is(name) && !rbx.is(value));
__ PopReturnAddressTo(rbx);
__ PopReturnAddressTo(temp);
__ Push(receiver);
__ Push(name);
__ Push(value);
__ PushReturnAddressFrom(rbx);
if (FLAG_vector_stores) {
Register slot = VectorStoreICDescriptor::SlotRegister();
Register vector = VectorStoreICDescriptor::VectorRegister();
DCHECK(!temp.is(slot) && !temp.is(vector));
__ Push(slot);
__ Push(vector);
}
__ PushReturnAddressFrom(temp);
}
@ -769,7 +776,8 @@ void StoreIC::GenerateMiss(MacroAssembler* masm) {
StoreIC_PushArgs(masm);
// Perform tail call to the entry.
__ TailCallRuntime(Runtime::kStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kStoreIC_Miss, args, 1);
}
@ -798,7 +806,8 @@ void KeyedStoreIC::GenerateMiss(MacroAssembler* masm) {
StoreIC_PushArgs(masm);
// Do tail-call to runtime routine.
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, 3, 1);
int args = FLAG_vector_stores ? 5 : 3;
__ TailCallRuntime(Runtime::kKeyedStoreIC_Miss, args, 1);
}

11
src/mips/macro-assembler-mips.h
View File

@ -674,6 +674,17 @@ class MacroAssembler: public Assembler {
sw(src4, MemOperand(sp, 0 * kPointerSize));
}
// Push five registers. Pushes leftmost register first (to highest address).
void Push(Register src1, Register src2, Register src3, Register src4,
Register src5) {
Subu(sp, sp, Operand(5 * kPointerSize));
sw(src1, MemOperand(sp, 4 * kPointerSize));
sw(src2, MemOperand(sp, 3 * kPointerSize));
sw(src3, MemOperand(sp, 2 * kPointerSize));
sw(src4, MemOperand(sp, 1 * kPointerSize));
sw(src5, MemOperand(sp, 0 * kPointerSize));
}
void Push(Register src, Condition cond, Register tst1, Register tst2) {
// Since we don't have conditional execution we use a Branch.
Branch(3, cond, tst1, Operand(tst2));

11
src/mips64/macro-assembler-mips64.h
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@ -699,6 +699,17 @@ class MacroAssembler: public Assembler {
sd(src4, MemOperand(sp, 0 * kPointerSize));
}
// Push five registers. Pushes leftmost register first (to highest address).
void Push(Register src1, Register src2, Register src3, Register src4,
Register src5) {
Dsubu(sp, sp, Operand(5 * kPointerSize));
sd(src1, MemOperand(sp, 4 * kPointerSize));
sd(src2, MemOperand(sp, 3 * kPointerSize));
sd(src3, MemOperand(sp, 2 * kPointerSize));
sd(src4, MemOperand(sp, 1 * kPointerSize));
sd(src5, MemOperand(sp, 0 * kPointerSize));
}
void Push(Register src, Condition cond, Register tst1, Register tst2) {
// Since we don't have conditional execution we use a Branch.
Branch(3, cond, tst1, Operand(tst2));