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[mips][wasm-simd] Implement i64x2 neg

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port a7b9e58 https://crrev.com/c/1900661

Original Commit Message:

  [wasm-simd] Implement i64x2 neg for arm

Change-Id: Ia4f52b26e4c3d6e2833b01246bd917d5e62ca79d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1924003
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Bill Budge <bbudge@chromium.org>
Auto-Submit: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#65103}
This commit is contained in:
Zhao Jiazhong 2019-11-20 03:56:34 -05:00 committed by Commit Bot
parent 31fab144f0
commit aadcef1cac
8 changed files with 20 additions and 0 deletions
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7
src/compiler/backend/mips/code-generator-mips.cc
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@ -2041,6 +2041,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ insert_w(dst, i.InputInt8(1) * 2 + 1, kScratchReg);
break;
}
case kMipsI64x2Neg: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ subv_d(i.OutputSimd128Register(), kSimd128RegZero,
i.InputSimd128Register(0));
break;
}
case kMipsF32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

1
src/compiler/backend/mips/instruction-codes-mips.h
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@ -153,6 +153,7 @@ namespace compiler {
V(MipsF64x2Ne) \
V(MipsF64x2Lt) \
V(MipsF64x2Le) \
V(MipsI64x2Neg) \
V(MipsF32x4Splat) \
V(MipsF32x4ExtractLane) \
V(MipsF32x4ReplaceLane) \

1
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -55,6 +55,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF64x2Splat:
case kMipsF64x2ExtractLane:
case kMipsF64x2ReplaceLane:
case kMipsI64x2Neg:
case kMipsF32x4Abs:
case kMipsF32x4Add:
case kMipsF32x4AddHoriz:

1
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2033,6 +2033,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Abs, kMipsF64x2Abs) \
V(F64x2Neg, kMipsF64x2Neg) \
V(F64x2Sqrt, kMipsF64x2Sqrt) \
V(I64x2Neg, kMipsI64x2Neg) \
V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \
V(F32x4Abs, kMipsF32x4Abs) \

7
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -2146,6 +2146,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ insert_d(dst, i.InputInt8(1), kScratchReg);
break;
}
case kMips64I64x2Neg: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ subv_d(i.OutputSimd128Register(), kSimd128RegZero,
i.InputSimd128Register(0));
break;
}
case kMips64F32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

1
src/compiler/backend/mips64/instruction-codes-mips64.h
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@ -201,6 +201,7 @@ namespace compiler {
V(Mips64F64x2Splat) \
V(Mips64F64x2ExtractLane) \
V(Mips64F64x2ReplaceLane) \
V(Mips64I64x2Neg) \
V(Mips64F32x4Abs) \
V(Mips64F32x4Neg) \
V(Mips64F32x4Sqrt) \

1
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -80,6 +80,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F64x2Ne:
case kMips64F64x2Lt:
case kMips64F64x2Le:
case kMips64I64x2Neg:
case kMips64F32x4Abs:
case kMips64F32x4Add:
case kMips64F32x4AddHoriz:

1
src/compiler/backend/mips64/instruction-selector-mips64.cc
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@ -2700,6 +2700,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Abs, kMips64F64x2Abs) \
V(F64x2Neg, kMips64F64x2Neg) \
V(F64x2Sqrt, kMips64F64x2Sqrt) \
V(I64x2Neg, kMips64I64x2Neg) \
V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4) \
V(F32x4Abs, kMips64F32x4Abs) \