ppc: [liftoff] optimize FillStackSlotsWithZero
Change-Id: Ic2576da8adff6935758ecae14ce5441d8af6428b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3075123 Reviewed-by: Milad Fa <mfarazma@redhat.com> Commit-Queue: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/master@{#76121}
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@ -691,40 +691,40 @@ void LiftoffAssembler::FillI64Half(Register, int offset, RegPairHalf) {
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void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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DCHECK_LT(0, size);
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DCHECK_EQ(0, size % 4);
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DCHECK_EQ(0, size % 8);
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RecordUsedSpillOffset(start + size);
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// We need a zero reg. Always use r0 for that, and push it before to restore
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// its value afterwards.
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push(r0);
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mov(r0, Operand(0));
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if (size <= 36) {
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// Special straight-line code for up to nine words. Generates one
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// instruction per word.
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for (int offset = 4; offset <= size; offset += 4) {
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StoreU64(r0, liftoff::GetHalfStackSlot(start + offset, kLowWord));
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mov(ip, Operand::Zero());
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uint32_t remainder = size;
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for (; remainder >= kStackSlotSize; remainder -= kStackSlotSize) {
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StoreU64(ip, liftoff::GetStackSlot(start + remainder), r0);
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}
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DCHECK(remainder == 4 || remainder == 0);
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if (remainder) {
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StoreU32(ip, liftoff::GetStackSlot(start + remainder), r0);
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}
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} else {
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// General case for bigger counts (9 instructions).
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// Use r4 for start address (inclusive), r5 for end address (exclusive).
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push(r4);
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push(r5);
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SubS64(r4, fp, Operand(start + size), r0);
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SubS64(r5, fp, Operand(start), r0);
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Label loop;
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push(r4);
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mov(r4, Operand(size / kSystemPointerSize));
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mtctr(r4);
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SubS64(r4, fp, Operand(start + size + kSystemPointerSize), r0);
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mov(r0, Operand::Zero());
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bind(&loop);
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StoreU64(r0, MemOperand(r0));
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addi(r0, r0, Operand(kSystemPointerSize));
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CmpS64(r4, r5);
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bne(&loop);
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StoreU64WithUpdate(r0, MemOperand(r4, kSystemPointerSize));
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bdnz(&loop);
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pop(r4);
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pop(r5);
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}
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pop(r0);
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}
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#define SIGN_EXT(r) extsw(r, r)
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