Fix LoadSpillAddress on big endian
BE machines use a 4 byte bias to spill/fill 32-bit values on the stack. This is done so because TF always fills 64-bit values even if the spilled value was 32-bits. To make sure this holds between LO and TF we have added a 4 byte bias in this CL: crrev.com/c/2756712 LoadSpillAddress needs to also take this into account and add a bias if the spilled value was 4 bytes. Change-Id: Ibd2b2071ce1fb11a9c5884611ae8edd1f17cb0c9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3891196 Commit-Queue: Milad Farazmand <mfarazma@redhat.com> Reviewed-by: Thibaud Michaud <thibaudm@chromium.org> Cr-Commit-Position: refs/heads/main@{#83163}
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@ -1550,7 +1550,8 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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pop(r0);
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}
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset) {
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset,
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ValueKind /* kind */) {
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sub(dst, fp, Operand(offset));
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}
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@ -1033,7 +1033,8 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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}
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}
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset) {
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset,
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ValueKind /* kind */) {
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Sub(dst, fp, offset);
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}
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@ -1286,7 +1286,8 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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}
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}
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset) {
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset,
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ValueKind /* kind */) {
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lea(dst, liftoff::GetStackSlot(offset));
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}
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@ -658,7 +658,7 @@ class LiftoffAssembler : public TurboAssembler {
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void Spill(VarState* slot);
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void SpillLocals();
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void SpillAllRegisters();
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inline void LoadSpillAddress(Register dst, int offset);
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inline void LoadSpillAddress(Register dst, int offset, ValueKind kind);
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// Clear any uses of {reg} in both the cache and in {possible_uses}.
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// Any use in the stack is spilled. If any register in {possible_uses} matches
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@ -2360,7 +2360,7 @@ class LiftoffCompiler {
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__ Spill(&return_slot);
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}
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DCHECK(return_slot.is_stack());
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__ LoadSpillAddress(param_reg, return_slot.offset());
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__ LoadSpillAddress(param_reg, return_slot.offset(), return_slot.kind());
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}
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source_position_table_builder_.AddPosition(
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@ -1093,7 +1093,9 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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}
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}
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset) {
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset,
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ValueKind kind) {
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if (kind == kI32) offset = offset + stack_bias;
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SubS64(dst, fp, Operand(offset));
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}
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@ -157,7 +157,8 @@ void LiftoffAssembler::PatchPrepareStackFrame(
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GenPCRelativeJump(kScratchReg, imm32);
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}
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset) {
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset,
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ValueKind /* kind */) {
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SubWord(dst, fp, offset);
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}
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@ -1552,7 +1552,9 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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pop(r0);
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}
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset) {
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset,
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ValueKind kind) {
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if (kind == kI32) offset = offset + stack_bias;
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SubS64(dst, fp, Operand(offset));
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}
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@ -1018,7 +1018,8 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
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}
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}
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset) {
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void LiftoffAssembler::LoadSpillAddress(Register dst, int offset,
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ValueKind /* kind */) {
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leaq(dst, liftoff::GetStackSlot(offset));
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}
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