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PPC: [compiler] Round result of float32 operations.

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R=joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1830723003

Cr-Commit-Position: refs/heads/master@{#35062}
This commit is contained in:
mbrandy 2016-03-24 10:17:27 -07:00 committed by Commit bot
parent 1a272ba23e
commit ad3cef5911
2 changed files with 41 additions and 37 deletions
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36
src/compiler/ppc/code-generator-ppc.cc
View File

@ -297,20 +297,24 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
} // namespace } // namespace
#define ASSEMBLE_FLOAT_UNOP_RC(asm_instr) \ #define ASSEMBLE_FLOAT_UNOP_RC(asm_instr, round) \
do { \ do { \
__ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), \ __ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), \
i.OutputRCBit()); \ i.OutputRCBit()); \
if (round) { \
__ frsp(i.OutputDoubleRegister(), i.OutputDoubleRegister()); \
} \
} while (0) } while (0)
#define ASSEMBLE_FLOAT_BINOP_RC(asm_instr, round) \
#define ASSEMBLE_FLOAT_BINOP_RC(asm_instr) \
do { \ do { \
__ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), \ __ asm_instr(i.OutputDoubleRegister(), i.InputDoubleRegister(0), \
i.InputDoubleRegister(1), i.OutputRCBit()); \ i.InputDoubleRegister(1), i.OutputRCBit()); \
if (round) { \
__ frsp(i.OutputDoubleRegister(), i.OutputDoubleRegister()); \
} \
} while (0) } while (0)
#define ASSEMBLE_BINOP(asm_instr_reg, asm_instr_imm) \ #define ASSEMBLE_BINOP(asm_instr_reg, asm_instr_imm) \
do { \ do { \
if (HasRegisterInput(instr, 1)) { \ if (HasRegisterInput(instr, 1)) { \
@ -1085,7 +1089,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
ASSEMBLE_ADD_WITH_OVERFLOW32(); ASSEMBLE_ADD_WITH_OVERFLOW32();
break; break;
case kPPC_AddDouble: case kPPC_AddDouble:
ASSEMBLE_FLOAT_BINOP_RC(fadd); ASSEMBLE_FLOAT_BINOP_RC(fadd, MiscField::decode(instr->opcode()));
break; break;
case kPPC_Sub: case kPPC_Sub:
#if V8_TARGET_ARCH_PPC64 #if V8_TARGET_ARCH_PPC64
@ -1108,7 +1112,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
ASSEMBLE_SUB_WITH_OVERFLOW32(); ASSEMBLE_SUB_WITH_OVERFLOW32();
break; break;
case kPPC_SubDouble: case kPPC_SubDouble:
ASSEMBLE_FLOAT_BINOP_RC(fsub); ASSEMBLE_FLOAT_BINOP_RC(fsub, MiscField::decode(instr->opcode()));
break; break;
case kPPC_Mul32: case kPPC_Mul32:
__ mullw(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1), __ mullw(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1),
@ -1129,7 +1133,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
i.OutputRCBit()); i.OutputRCBit());
break; break;
case kPPC_MulDouble: case kPPC_MulDouble:
ASSEMBLE_FLOAT_BINOP_RC(fmul); ASSEMBLE_FLOAT_BINOP_RC(fmul, MiscField::decode(instr->opcode()));
break; break;
case kPPC_Div32: case kPPC_Div32:
__ divw(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); __ divw(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
@ -1152,7 +1156,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break; break;
#endif #endif
case kPPC_DivDouble: case kPPC_DivDouble:
ASSEMBLE_FLOAT_BINOP_RC(fdiv); ASSEMBLE_FLOAT_BINOP_RC(fdiv, MiscField::decode(instr->opcode()));
break; break;
case kPPC_Mod32: case kPPC_Mod32:
ASSEMBLE_MODULO(divw, mullw); ASSEMBLE_MODULO(divw, mullw);
@ -1185,25 +1189,25 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
ASSEMBLE_FLOAT_MIN(kScratchDoubleReg); ASSEMBLE_FLOAT_MIN(kScratchDoubleReg);
break; break;
case kPPC_AbsDouble: case kPPC_AbsDouble:
ASSEMBLE_FLOAT_UNOP_RC(fabs); ASSEMBLE_FLOAT_UNOP_RC(fabs, 0);
break; break;
case kPPC_SqrtDouble: case kPPC_SqrtDouble:
ASSEMBLE_FLOAT_UNOP_RC(fsqrt); ASSEMBLE_FLOAT_UNOP_RC(fsqrt, MiscField::decode(instr->opcode()));
break; break;
case kPPC_FloorDouble: case kPPC_FloorDouble:
ASSEMBLE_FLOAT_UNOP_RC(frim); ASSEMBLE_FLOAT_UNOP_RC(frim, MiscField::decode(instr->opcode()));
break; break;
case kPPC_CeilDouble: case kPPC_CeilDouble:
ASSEMBLE_FLOAT_UNOP_RC(frip); ASSEMBLE_FLOAT_UNOP_RC(frip, MiscField::decode(instr->opcode()));
break; break;
case kPPC_TruncateDouble: case kPPC_TruncateDouble:
ASSEMBLE_FLOAT_UNOP_RC(friz); ASSEMBLE_FLOAT_UNOP_RC(friz, MiscField::decode(instr->opcode()));
break; break;
case kPPC_RoundDouble: case kPPC_RoundDouble:
ASSEMBLE_FLOAT_UNOP_RC(frin); ASSEMBLE_FLOAT_UNOP_RC(frin, MiscField::decode(instr->opcode()));
break; break;
case kPPC_NegDouble: case kPPC_NegDouble:
ASSEMBLE_FLOAT_UNOP_RC(fneg); ASSEMBLE_FLOAT_UNOP_RC(fneg, 0);
break; break;
case kPPC_Cntlz32: case kPPC_Cntlz32:
__ cntlzw_(i.OutputRegister(), i.InputRegister(0)); __ cntlzw_(i.OutputRegister(), i.InputRegister(0));
@ -1409,7 +1413,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
} }
#endif #endif
case kPPC_DoubleToFloat32: case kPPC_DoubleToFloat32:
ASSEMBLE_FLOAT_UNOP_RC(frsp); ASSEMBLE_FLOAT_UNOP_RC(frsp, 0);
break; break;
case kPPC_Float32ToDouble: case kPPC_Float32ToDouble:
// Nothing to do. // Nothing to do.

42
src/compiler/ppc/instruction-selector-ppc.cc
View File

@ -71,22 +71,22 @@ class PPCOperandGenerator final : public OperandGenerator {
namespace { namespace {
void VisitRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) { void VisitRR(InstructionSelector* selector, InstructionCode opcode,
Node* node) {
PPCOperandGenerator g(selector); PPCOperandGenerator g(selector);
selector->Emit(opcode, g.DefineAsRegister(node), selector->Emit(opcode, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0))); g.UseRegister(node->InputAt(0)));
} }
void VisitRRR(InstructionSelector* selector, InstructionCode opcode,
void VisitRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) { Node* node) {
PPCOperandGenerator g(selector); PPCOperandGenerator g(selector);
selector->Emit(opcode, g.DefineAsRegister(node), selector->Emit(opcode, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1))); g.UseRegister(node->InputAt(1)));
} }
void VisitRRO(InstructionSelector* selector, InstructionCode opcode, Node* node,
void VisitRRO(InstructionSelector* selector, ArchOpcode opcode, Node* node,
ImmediateMode operand_mode) { ImmediateMode operand_mode) {
PPCOperandGenerator g(selector); PPCOperandGenerator g(selector);
selector->Emit(opcode, g.DefineAsRegister(node), selector->Emit(opcode, g.DefineAsRegister(node),
@ -96,8 +96,8 @@ void VisitRRO(InstructionSelector* selector, ArchOpcode opcode, Node* node,
#if V8_TARGET_ARCH_PPC64 #if V8_TARGET_ARCH_PPC64
void VisitTryTruncateDouble(InstructionSelector* selector, ArchOpcode opcode, void VisitTryTruncateDouble(InstructionSelector* selector,
Node* node) { InstructionCode opcode, Node* node) {
PPCOperandGenerator g(selector); PPCOperandGenerator g(selector);
InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))};
InstructionOperand outputs[2]; InstructionOperand outputs[2];
@ -156,8 +156,8 @@ void VisitBinop(InstructionSelector* selector, Node* node,
// Shared routine for multiple binary operations. // Shared routine for multiple binary operations.
template <typename Matcher> template <typename Matcher>
void VisitBinop(InstructionSelector* selector, Node* node, ArchOpcode opcode, void VisitBinop(InstructionSelector* selector, Node* node,
ImmediateMode operand_mode) { InstructionCode opcode, ImmediateMode operand_mode) {
FlagsContinuation cont; FlagsContinuation cont;
VisitBinop<Matcher>(selector, node, opcode, operand_mode, &cont); VisitBinop<Matcher>(selector, node, opcode, operand_mode, &cont);
} }
@ -785,7 +785,7 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
} }
#if !V8_TARGET_ARCH_PPC64 #if !V8_TARGET_ARCH_PPC64
void VisitPairBinop(InstructionSelector* selector, ArchOpcode opcode, void VisitPairBinop(InstructionSelector* selector, InstructionCode opcode,
Node* node) { Node* node) {
PPCOperandGenerator g(selector); PPCOperandGenerator g(selector);
@ -810,7 +810,7 @@ void InstructionSelector::VisitInt32PairSub(Node* node) {
VisitPairBinop(this, kPPC_SubPair, node); VisitPairBinop(this, kPPC_SubPair, node);
} }
void VisitPairShift(InstructionSelector* selector, ArchOpcode opcode, void VisitPairShift(InstructionSelector* selector, InstructionCode opcode,
Node* node) { Node* node) {
PPCOperandGenerator g(selector); PPCOperandGenerator g(selector);
Int32Matcher m(node->InputAt(2)); Int32Matcher m(node->InputAt(2));
@ -1169,7 +1169,7 @@ void InstructionSelector::VisitBitcastInt64ToFloat64(Node* node) {
void InstructionSelector::VisitFloat32Add(Node* node) { void InstructionSelector::VisitFloat32Add(Node* node) {
VisitRRR(this, kPPC_AddDouble, node); VisitRRR(this, kPPC_AddDouble | MiscField::encode(1), node);
} }
@ -1183,11 +1183,11 @@ void InstructionSelector::VisitFloat32Sub(Node* node) {
PPCOperandGenerator g(this); PPCOperandGenerator g(this);
Float32BinopMatcher m(node); Float32BinopMatcher m(node);
if (m.left().IsMinusZero()) { if (m.left().IsMinusZero()) {
Emit(kPPC_NegDouble, g.DefineAsRegister(node), Emit(kPPC_NegDouble | MiscField::encode(1), g.DefineAsRegister(node),
g.UseRegister(m.right().node())); g.UseRegister(m.right().node()));
return; return;
} }
VisitRRR(this, kPPC_SubDouble, node); VisitRRR(this, kPPC_SubDouble | MiscField::encode(1), node);
} }
@ -1218,7 +1218,7 @@ void InstructionSelector::VisitFloat64Sub(Node* node) {
void InstructionSelector::VisitFloat32Mul(Node* node) { void InstructionSelector::VisitFloat32Mul(Node* node) {
VisitRRR(this, kPPC_MulDouble, node); VisitRRR(this, kPPC_MulDouble | MiscField::encode(1), node);
} }
@ -1229,7 +1229,7 @@ void InstructionSelector::VisitFloat64Mul(Node* node) {
void InstructionSelector::VisitFloat32Div(Node* node) { void InstructionSelector::VisitFloat32Div(Node* node) {
VisitRRR(this, kPPC_DivDouble, node); VisitRRR(this, kPPC_DivDouble | MiscField::encode(1), node);
} }
@ -1259,7 +1259,7 @@ void InstructionSelector::VisitFloat64Min(Node* node) { UNREACHABLE(); }
void InstructionSelector::VisitFloat32Abs(Node* node) { void InstructionSelector::VisitFloat32Abs(Node* node) {
VisitRR(this, kPPC_AbsDouble, node); VisitRR(this, kPPC_AbsDouble | MiscField::encode(1), node);
} }
@ -1269,7 +1269,7 @@ void InstructionSelector::VisitFloat64Abs(Node* node) {
void InstructionSelector::VisitFloat32Sqrt(Node* node) { void InstructionSelector::VisitFloat32Sqrt(Node* node) {
VisitRR(this, kPPC_SqrtDouble, node); VisitRR(this, kPPC_SqrtDouble | MiscField::encode(1), node);
} }
@ -1279,7 +1279,7 @@ void InstructionSelector::VisitFloat64Sqrt(Node* node) {
void InstructionSelector::VisitFloat32RoundDown(Node* node) { void InstructionSelector::VisitFloat32RoundDown(Node* node) {
VisitRR(this, kPPC_FloorDouble, node); VisitRR(this, kPPC_FloorDouble | MiscField::encode(1), node);
} }
@ -1289,7 +1289,7 @@ void InstructionSelector::VisitFloat64RoundDown(Node* node) {
void InstructionSelector::VisitFloat32RoundUp(Node* node) { void InstructionSelector::VisitFloat32RoundUp(Node* node) {
VisitRR(this, kPPC_CeilDouble, node); VisitRR(this, kPPC_CeilDouble | MiscField::encode(1), node);
} }
@ -1299,7 +1299,7 @@ void InstructionSelector::VisitFloat64RoundUp(Node* node) {
void InstructionSelector::VisitFloat32RoundTruncate(Node* node) { void InstructionSelector::VisitFloat32RoundTruncate(Node* node) {
VisitRR(this, kPPC_TruncateDouble, node); VisitRR(this, kPPC_TruncateDouble | MiscField::encode(1), node);
} }