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[wasm-simd] Implement rounding average for arm64

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Bug: v8:10039
Change-Id: Ic2775bfcae330ff9763bc28a65a806e6a41a5fba
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1958013
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65543}
This commit is contained in:
Ng Zhi An 2019-12-19 15:57:08 -08:00 committed by Commit Bot
parent 38f39a01ff
commit b1840ab9f6
6 changed files with 98 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/compiler/backend/arm64/code-generator-arm64.cc
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@ -2248,6 +2248,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_BINOP_CASE(kArm64I16x8MaxU, Umax, 8H);
SIMD_BINOP_CASE(kArm64I16x8GtU, Cmhi, 8H);
SIMD_BINOP_CASE(kArm64I16x8GeU, Cmhs, 8H);
SIMD_BINOP_CASE(kArm64I16x8RoundingAverageU, Urhadd, 8H);
case kArm64I8x16Splat: {
__ Dup(i.OutputSimd128Register().V16B(), i.InputRegister32(0));
break;
@ -2355,6 +2356,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_BINOP_CASE(kArm64I8x16MaxU, Umax, 16B);
SIMD_BINOP_CASE(kArm64I8x16GtU, Cmhi, 16B);
SIMD_BINOP_CASE(kArm64I8x16GeU, Cmhs, 16B);
SIMD_BINOP_CASE(kArm64I8x16RoundingAverageU, Urhadd, 16B);
case kArm64S128Zero: {
__ Movi(i.OutputSimd128Register().V16B(), 0);
break;

2
src/compiler/backend/arm64/instruction-codes-arm64.h
View File

@ -284,6 +284,7 @@ namespace compiler {
V(Arm64I16x8MaxU) \
V(Arm64I16x8GtU) \
V(Arm64I16x8GeU) \
V(Arm64I16x8RoundingAverageU) \
V(Arm64I8x16Splat) \
V(Arm64I8x16ExtractLaneU) \
V(Arm64I8x16ExtractLaneS) \
@ -311,6 +312,7 @@ namespace compiler {
V(Arm64I8x16MaxU) \
V(Arm64I8x16GtU) \
V(Arm64I8x16GeU) \
V(Arm64I8x16RoundingAverageU) \
V(Arm64S128Zero) \
V(Arm64S128Dup) \
V(Arm64S128And) \

2
src/compiler/backend/arm64/instruction-scheduler-arm64.cc
View File

@ -254,6 +254,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64I16x8MaxU:
case kArm64I16x8GtU:
case kArm64I16x8GeU:
case kArm64I16x8RoundingAverageU:
case kArm64I8x16Splat:
case kArm64I8x16ExtractLaneU:
case kArm64I8x16ExtractLaneS:
@ -281,6 +282,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64I8x16MaxU:
case kArm64I8x16GtU:
case kArm64I8x16GeU:
case kArm64I8x16RoundingAverageU:
case kArm64S128Zero:
case kArm64S128Dup:
case kArm64S128And:

172
src/compiler/backend/arm64/instruction-selector-arm64.cc
View File

@ -3175,91 +3175,93 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16ShrS) \
V(I8x16ShrU)
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, kArm64F64x2Add) \
V(F64x2Sub, kArm64F64x2Sub) \
V(F64x2Mul, kArm64F64x2Mul) \
V(F64x2Div, kArm64F64x2Div) \
V(F64x2Min, kArm64F64x2Min) \
V(F64x2Max, kArm64F64x2Max) \
V(F64x2Eq, kArm64F64x2Eq) \
V(F64x2Ne, kArm64F64x2Ne) \
V(F64x2Lt, kArm64F64x2Lt) \
V(F64x2Le, kArm64F64x2Le) \
V(F32x4Add, kArm64F32x4Add) \
V(F32x4AddHoriz, kArm64F32x4AddHoriz) \
V(F32x4Sub, kArm64F32x4Sub) \
V(F32x4Mul, kArm64F32x4Mul) \
V(F32x4Div, kArm64F32x4Div) \
V(F32x4Min, kArm64F32x4Min) \
V(F32x4Max, kArm64F32x4Max) \
V(F32x4Eq, kArm64F32x4Eq) \
V(F32x4Ne, kArm64F32x4Ne) \
V(F32x4Lt, kArm64F32x4Lt) \
V(F32x4Le, kArm64F32x4Le) \
V(I64x2Add, kArm64I64x2Add) \
V(I64x2Sub, kArm64I64x2Sub) \
V(I64x2Eq, kArm64I64x2Eq) \
V(I64x2Ne, kArm64I64x2Ne) \
V(I64x2GtS, kArm64I64x2GtS) \
V(I64x2GeS, kArm64I64x2GeS) \
V(I64x2GtU, kArm64I64x2GtU) \
V(I64x2GeU, kArm64I64x2GeU) \
V(I32x4Add, kArm64I32x4Add) \
V(I32x4AddHoriz, kArm64I32x4AddHoriz) \
V(I32x4Sub, kArm64I32x4Sub) \
V(I32x4Mul, kArm64I32x4Mul) \
V(I32x4MinS, kArm64I32x4MinS) \
V(I32x4MaxS, kArm64I32x4MaxS) \
V(I32x4Eq, kArm64I32x4Eq) \
V(I32x4Ne, kArm64I32x4Ne) \
V(I32x4GtS, kArm64I32x4GtS) \
V(I32x4GeS, kArm64I32x4GeS) \
V(I32x4MinU, kArm64I32x4MinU) \
V(I32x4MaxU, kArm64I32x4MaxU) \
V(I32x4GtU, kArm64I32x4GtU) \
V(I32x4GeU, kArm64I32x4GeU) \
V(I16x8SConvertI32x4, kArm64I16x8SConvertI32x4) \
V(I16x8Add, kArm64I16x8Add) \
V(I16x8AddSaturateS, kArm64I16x8AddSaturateS) \
V(I16x8AddHoriz, kArm64I16x8AddHoriz) \
V(I16x8Sub, kArm64I16x8Sub) \
V(I16x8SubSaturateS, kArm64I16x8SubSaturateS) \
V(I16x8Mul, kArm64I16x8Mul) \
V(I16x8MinS, kArm64I16x8MinS) \
V(I16x8MaxS, kArm64I16x8MaxS) \
V(I16x8Eq, kArm64I16x8Eq) \
V(I16x8Ne, kArm64I16x8Ne) \
V(I16x8GtS, kArm64I16x8GtS) \
V(I16x8GeS, kArm64I16x8GeS) \
V(I16x8UConvertI32x4, kArm64I16x8UConvertI32x4) \
V(I16x8AddSaturateU, kArm64I16x8AddSaturateU) \
V(I16x8SubSaturateU, kArm64I16x8SubSaturateU) \
V(I16x8MinU, kArm64I16x8MinU) \
V(I16x8MaxU, kArm64I16x8MaxU) \
V(I16x8GtU, kArm64I16x8GtU) \
V(I16x8GeU, kArm64I16x8GeU) \
V(I8x16SConvertI16x8, kArm64I8x16SConvertI16x8) \
V(I8x16Add, kArm64I8x16Add) \
V(I8x16AddSaturateS, kArm64I8x16AddSaturateS) \
V(I8x16Sub, kArm64I8x16Sub) \
V(I8x16SubSaturateS, kArm64I8x16SubSaturateS) \
V(I8x16Mul, kArm64I8x16Mul) \
V(I8x16MinS, kArm64I8x16MinS) \
V(I8x16MaxS, kArm64I8x16MaxS) \
V(I8x16Eq, kArm64I8x16Eq) \
V(I8x16Ne, kArm64I8x16Ne) \
V(I8x16GtS, kArm64I8x16GtS) \
V(I8x16GeS, kArm64I8x16GeS) \
V(I8x16UConvertI16x8, kArm64I8x16UConvertI16x8) \
V(I8x16AddSaturateU, kArm64I8x16AddSaturateU) \
V(I8x16SubSaturateU, kArm64I8x16SubSaturateU) \
V(I8x16MinU, kArm64I8x16MinU) \
V(I8x16MaxU, kArm64I8x16MaxU) \
V(I8x16GtU, kArm64I8x16GtU) \
V(I8x16GeU, kArm64I8x16GeU) \
V(S128And, kArm64S128And) \
V(S128Or, kArm64S128Or) \
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, kArm64F64x2Add) \
V(F64x2Sub, kArm64F64x2Sub) \
V(F64x2Mul, kArm64F64x2Mul) \
V(F64x2Div, kArm64F64x2Div) \
V(F64x2Min, kArm64F64x2Min) \
V(F64x2Max, kArm64F64x2Max) \
V(F64x2Eq, kArm64F64x2Eq) \
V(F64x2Ne, kArm64F64x2Ne) \
V(F64x2Lt, kArm64F64x2Lt) \
V(F64x2Le, kArm64F64x2Le) \
V(F32x4Add, kArm64F32x4Add) \
V(F32x4AddHoriz, kArm64F32x4AddHoriz) \
V(F32x4Sub, kArm64F32x4Sub) \
V(F32x4Mul, kArm64F32x4Mul) \
V(F32x4Div, kArm64F32x4Div) \
V(F32x4Min, kArm64F32x4Min) \
V(F32x4Max, kArm64F32x4Max) \
V(F32x4Eq, kArm64F32x4Eq) \
V(F32x4Ne, kArm64F32x4Ne) \
V(F32x4Lt, kArm64F32x4Lt) \
V(F32x4Le, kArm64F32x4Le) \
V(I64x2Add, kArm64I64x2Add) \
V(I64x2Sub, kArm64I64x2Sub) \
V(I64x2Eq, kArm64I64x2Eq) \
V(I64x2Ne, kArm64I64x2Ne) \
V(I64x2GtS, kArm64I64x2GtS) \
V(I64x2GeS, kArm64I64x2GeS) \
V(I64x2GtU, kArm64I64x2GtU) \
V(I64x2GeU, kArm64I64x2GeU) \
V(I32x4Add, kArm64I32x4Add) \
V(I32x4AddHoriz, kArm64I32x4AddHoriz) \
V(I32x4Sub, kArm64I32x4Sub) \
V(I32x4Mul, kArm64I32x4Mul) \
V(I32x4MinS, kArm64I32x4MinS) \
V(I32x4MaxS, kArm64I32x4MaxS) \
V(I32x4Eq, kArm64I32x4Eq) \
V(I32x4Ne, kArm64I32x4Ne) \
V(I32x4GtS, kArm64I32x4GtS) \
V(I32x4GeS, kArm64I32x4GeS) \
V(I32x4MinU, kArm64I32x4MinU) \
V(I32x4MaxU, kArm64I32x4MaxU) \
V(I32x4GtU, kArm64I32x4GtU) \
V(I32x4GeU, kArm64I32x4GeU) \
V(I16x8SConvertI32x4, kArm64I16x8SConvertI32x4) \
V(I16x8Add, kArm64I16x8Add) \
V(I16x8AddSaturateS, kArm64I16x8AddSaturateS) \
V(I16x8AddHoriz, kArm64I16x8AddHoriz) \
V(I16x8Sub, kArm64I16x8Sub) \
V(I16x8SubSaturateS, kArm64I16x8SubSaturateS) \
V(I16x8Mul, kArm64I16x8Mul) \
V(I16x8MinS, kArm64I16x8MinS) \
V(I16x8MaxS, kArm64I16x8MaxS) \
V(I16x8Eq, kArm64I16x8Eq) \
V(I16x8Ne, kArm64I16x8Ne) \
V(I16x8GtS, kArm64I16x8GtS) \
V(I16x8GeS, kArm64I16x8GeS) \
V(I16x8UConvertI32x4, kArm64I16x8UConvertI32x4) \
V(I16x8AddSaturateU, kArm64I16x8AddSaturateU) \
V(I16x8SubSaturateU, kArm64I16x8SubSaturateU) \
V(I16x8MinU, kArm64I16x8MinU) \
V(I16x8MaxU, kArm64I16x8MaxU) \
V(I16x8GtU, kArm64I16x8GtU) \
V(I16x8GeU, kArm64I16x8GeU) \
V(I16x8RoundingAverageU, kArm64I16x8RoundingAverageU) \
V(I8x16SConvertI16x8, kArm64I8x16SConvertI16x8) \
V(I8x16Add, kArm64I8x16Add) \
V(I8x16AddSaturateS, kArm64I8x16AddSaturateS) \
V(I8x16Sub, kArm64I8x16Sub) \
V(I8x16SubSaturateS, kArm64I8x16SubSaturateS) \
V(I8x16Mul, kArm64I8x16Mul) \
V(I8x16MinS, kArm64I8x16MinS) \
V(I8x16MaxS, kArm64I8x16MaxS) \
V(I8x16Eq, kArm64I8x16Eq) \
V(I8x16Ne, kArm64I8x16Ne) \
V(I8x16GtS, kArm64I8x16GtS) \
V(I8x16GeS, kArm64I8x16GeS) \
V(I8x16UConvertI16x8, kArm64I8x16UConvertI16x8) \
V(I8x16AddSaturateU, kArm64I8x16AddSaturateU) \
V(I8x16SubSaturateU, kArm64I8x16SubSaturateU) \
V(I8x16MinU, kArm64I8x16MinU) \
V(I8x16MaxU, kArm64I8x16MaxU) \
V(I8x16GtU, kArm64I8x16GtU) \
V(I8x16GeU, kArm64I8x16GeU) \
V(I8x16RoundingAverageU, kArm64I8x16RoundingAverageU) \
V(S128And, kArm64S128And) \
V(S128Or, kArm64S128Or) \
V(S128Xor, kArm64S128Xor)
void InstructionSelector::VisitS128Zero(Node* node) {

2
src/compiler/backend/instruction-selector.cc
View File

@ -2634,13 +2634,13 @@ void InstructionSelector::VisitF64x2SConvertI64x2(Node* node) {
void InstructionSelector::VisitF64x2UConvertI64x2(Node* node) {
UNIMPLEMENTED();
}
#if !V8_TARGET_ARCH_ARM64
void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16RoundingAverageU(Node* node) {
UNIMPLEMENTED();
}
#if !V8_TARGET_ARCH_ARM64
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitLoadTransform(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM

8
test/cctest/wasm/test-run-wasm-simd.cc
View File

@ -2181,13 +2181,13 @@ WASM_SIMD_TEST(I16x8LeU) {
UnsignedLessEqual);
}
#if V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_TEST_NO_LOWERING(I16x8RoundingAverageU) {
RunI16x8BinOpTest<uint16_t>(execution_tier, lower_simd,
kExprI16x8RoundingAverageU,
base::RoundingAverageUnsigned);
}
#endif // V8_TARGET_ARCH_X64
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
void RunI16x8ShiftOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, Int16ShiftOp expected_op) {
@ -2407,13 +2407,13 @@ WASM_SIMD_TEST(I8x16Mul) {
base::MulWithWraparound);
}
#if V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_TEST_NO_LOWERING(I8x16RoundingAverageU) {
RunI8x16BinOpTest<uint8_t>(execution_tier, lower_simd,
kExprI8x16RoundingAverageU,
base::RoundingAverageUnsigned);
}
#endif // V8_TARGET_ARCH_X64
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
void RunI8x16ShiftOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, Int8ShiftOp expected_op) {