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[wasm-simd] Implement rounding average for arm64

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Bug: v8:10039
Change-Id: Ic2775bfcae330ff9763bc28a65a806e6a41a5fba
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1958013
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65543}
This commit is contained in:
Ng Zhi An 2019-12-19 15:57:08 -08:00 committed by Commit Bot
parent 38f39a01ff
commit b1840ab9f6
6 changed files with 98 additions and 90 deletions
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2
src/compiler/backend/arm64/code-generator-arm64.cc
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@ -2248,6 +2248,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_BINOP_CASE(kArm64I16x8MaxU, Umax, 8H);
SIMD_BINOP_CASE(kArm64I16x8GtU, Cmhi, 8H);
SIMD_BINOP_CASE(kArm64I16x8GeU, Cmhs, 8H);
SIMD_BINOP_CASE(kArm64I16x8RoundingAverageU, Urhadd, 8H);
case kArm64I8x16Splat: {
__ Dup(i.OutputSimd128Register().V16B(), i.InputRegister32(0));
break;
@ -2355,6 +2356,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_BINOP_CASE(kArm64I8x16MaxU, Umax, 16B);
SIMD_BINOP_CASE(kArm64I8x16GtU, Cmhi, 16B);
SIMD_BINOP_CASE(kArm64I8x16GeU, Cmhs, 16B);
SIMD_BINOP_CASE(kArm64I8x16RoundingAverageU, Urhadd, 16B);
case kArm64S128Zero: {
__ Movi(i.OutputSimd128Register().V16B(), 0);
break;

2
src/compiler/backend/arm64/instruction-codes-arm64.h
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@ -284,6 +284,7 @@ namespace compiler {
V(Arm64I16x8MaxU) \
V(Arm64I16x8GtU) \
V(Arm64I16x8GeU) \
V(Arm64I16x8RoundingAverageU) \
V(Arm64I8x16Splat) \
V(Arm64I8x16ExtractLaneU) \
V(Arm64I8x16ExtractLaneS) \
@ -311,6 +312,7 @@ namespace compiler {
V(Arm64I8x16MaxU) \
V(Arm64I8x16GtU) \
V(Arm64I8x16GeU) \
V(Arm64I8x16RoundingAverageU) \
V(Arm64S128Zero) \
V(Arm64S128Dup) \
V(Arm64S128And) \

2
src/compiler/backend/arm64/instruction-scheduler-arm64.cc
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@ -254,6 +254,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64I16x8MaxU:
case kArm64I16x8GtU:
case kArm64I16x8GeU:
case kArm64I16x8RoundingAverageU:
case kArm64I8x16Splat:
case kArm64I8x16ExtractLaneU:
case kArm64I8x16ExtractLaneS:
@ -281,6 +282,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64I8x16MaxU:
case kArm64I8x16GtU:
case kArm64I8x16GeU:
case kArm64I8x16RoundingAverageU:
case kArm64S128Zero:
case kArm64S128Dup:
case kArm64S128And:

2
src/compiler/backend/arm64/instruction-selector-arm64.cc
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@ -3239,6 +3239,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8MaxU, kArm64I16x8MaxU) \
V(I16x8GtU, kArm64I16x8GtU) \
V(I16x8GeU, kArm64I16x8GeU) \
V(I16x8RoundingAverageU, kArm64I16x8RoundingAverageU) \
V(I8x16SConvertI16x8, kArm64I8x16SConvertI16x8) \
V(I8x16Add, kArm64I8x16Add) \
V(I8x16AddSaturateS, kArm64I8x16AddSaturateS) \
@ -3258,6 +3259,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16MaxU, kArm64I8x16MaxU) \
V(I8x16GtU, kArm64I8x16GtU) \
V(I8x16GeU, kArm64I8x16GeU) \
V(I8x16RoundingAverageU, kArm64I8x16RoundingAverageU) \
V(S128And, kArm64S128And) \
V(S128Or, kArm64S128Or) \
V(S128Xor, kArm64S128Xor)

2
src/compiler/backend/instruction-selector.cc
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@ -2634,13 +2634,13 @@ void InstructionSelector::VisitF64x2SConvertI64x2(Node* node) {
void InstructionSelector::VisitF64x2UConvertI64x2(Node* node) {
UNIMPLEMENTED();
}
#if !V8_TARGET_ARCH_ARM64
void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16RoundingAverageU(Node* node) {
UNIMPLEMENTED();
}
#if !V8_TARGET_ARCH_ARM64
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitLoadTransform(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM

8
test/cctest/wasm/test-run-wasm-simd.cc
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@ -2181,13 +2181,13 @@ WASM_SIMD_TEST(I16x8LeU) {
UnsignedLessEqual);
}
#if V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_TEST_NO_LOWERING(I16x8RoundingAverageU) {
RunI16x8BinOpTest<uint16_t>(execution_tier, lower_simd,
kExprI16x8RoundingAverageU,
base::RoundingAverageUnsigned);
}
#endif // V8_TARGET_ARCH_X64
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
void RunI16x8ShiftOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, Int16ShiftOp expected_op) {
@ -2407,13 +2407,13 @@ WASM_SIMD_TEST(I8x16Mul) {
base::MulWithWraparound);
}
#if V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
WASM_SIMD_TEST_NO_LOWERING(I8x16RoundingAverageU) {
RunI8x16BinOpTest<uint8_t>(execution_tier, lower_simd,
kExprI8x16RoundingAverageU,
base::RoundingAverageUnsigned);
}
#endif // V8_TARGET_ARCH_X64
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
void RunI8x16ShiftOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, Int8ShiftOp expected_op) {