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[x64][ia32] Set lower SSE flags when newer extensions are enabled

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If SSE4.2 is enabled, all the previous extensions should also be
enabled. In particular, you cannot have --enable-sse4_1 and
--no-enable-sse3.

Bug: chromium:1195579
Change-Id: Id3e10db24cee2aee14449a77c9e7cff82e97edff
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2808621
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#73840}
This commit is contained in:
Ng Zhi An 2021-04-06 14:38:32 -07:00 committed by Commit Bot
parent baf2b088dd
commit b49638c524
2 changed files with 37 additions and 21 deletions
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24
src/codegen/ia32/assembler-ia32.cc
View File

@ -138,14 +138,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
// Only use statically determined features for cross compile (snapshot).
if (cross_compile) return;
if (cpu.has_sse42() && FLAG_enable_sse4_2) supported_ |= 1u << SSE4_2;
if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
if (cpu.has_ssse3() && FLAG_enable_ssse3) supported_ |= 1u << SSSE3;
if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
OSHasAVXSupport()) {
supported_ |= 1u << AVX;
}
// To deal with any combination of flags (e.g. --no-enable-sse4-1
// --enable-sse-4-2), we start checking from the "highest" supported
// extension, for each extension, enable if newer extension is supported.
if (cpu.has_avx2() && FLAG_enable_avx2 && IsSupported(AVX)) {
supported_ |= 1u << AVX2;
}
@ -153,6 +148,19 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
OSHasAVXSupport()) {
supported_ |= 1u << FMA3;
}
if ((cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
OSHasAVXSupport()) ||
IsSupported(AVX2) || IsSupported(FMA3)) {
supported_ |= 1u << AVX;
}
if ((cpu.has_sse42() && FLAG_enable_sse4_2) || IsSupported(AVX))
supported_ |= 1u << SSE4_2;
if ((cpu.has_sse41() && FLAG_enable_sse4_1) || IsSupported(SSE4_2))
supported_ |= 1u << SSE4_1;
if ((cpu.has_ssse3() && FLAG_enable_ssse3) || IsSupported(SSE4_1))
supported_ |= 1u << SSSE3;
if ((cpu.has_sse3() && FLAG_enable_sse3) || IsSupported(SSSE3))
supported_ |= 1u << SSE3;
if (cpu.has_bmi1() && FLAG_enable_bmi1) supported_ |= 1u << BMI1;
if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2;
if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT;

34
src/codegen/x64/assembler-x64.cc
View File

@ -87,19 +87,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
// Only use statically determined features for cross compile (snapshot).
if (cross_compile) return;
if (cpu.has_sse42() && FLAG_enable_sse4_2) supported_ |= 1u << SSE4_2;
if (cpu.has_sse41() && FLAG_enable_sse4_1) {
supported_ |= 1u << SSE4_1;
supported_ |= 1u << SSSE3;
}
if (cpu.has_ssse3() && FLAG_enable_ssse3) supported_ |= 1u << SSSE3;
if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
// SAHF is not generally available in long mode.
if (cpu.has_sahf() && FLAG_enable_sahf) supported_ |= 1u << SAHF;
if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
OSHasAVXSupport()) {
supported_ |= 1u << AVX;
}
// To deal with any combination of flags (e.g. --no-enable-sse4-1
// --enable-sse-4-2), we start checking from the "highest" supported
// extension, for each extension, enable if newer extension is supported.
if (cpu.has_avx2() && FLAG_enable_avx2 && IsSupported(AVX)) {
supported_ |= 1u << AVX2;
}
@ -107,6 +97,24 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
OSHasAVXSupport()) {
supported_ |= 1u << FMA3;
}
if ((cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
OSHasAVXSupport()) ||
IsSupported(AVX2) || IsSupported(FMA3)) {
supported_ |= 1u << AVX;
}
if ((cpu.has_sse42() && FLAG_enable_sse4_2) || IsSupported(AVX)) {
supported_ |= 1u << SSE4_2;
}
if ((cpu.has_sse41() && FLAG_enable_sse4_1) || IsSupported(SSE4_2)) {
supported_ |= 1u << SSE4_1;
}
if ((cpu.has_ssse3() && FLAG_enable_ssse3) || IsSupported(SSE4_1)) {
supported_ |= 1u << SSSE3;
}
if ((cpu.has_sse3() && FLAG_enable_sse3) || IsSupported(SSSE3))
supported_ |= 1u << SSE3;
// SAHF is not generally available in long mode.
if (cpu.has_sahf() && FLAG_enable_sahf) supported_ |= 1u << SAHF;
if (cpu.has_bmi1() && FLAG_enable_bmi1) supported_ |= 1u << BMI1;
if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2;
if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT;