AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

PPC/s390: [relaxed-simd] Fix ordering of relaxed FMA/FNMA operands

Browse Source 
Port b0c2b7797a

Original Commit Message:

    New ordering and rationale described here:
    https://github.com/WebAssembly/relaxed-simd/issues/27#issuecomment-1190859982

R=gdeepti@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com
BUG=
LOG=N

Change-Id: I551bcd97555ec8f9dd7a8840b88be6cc3670697c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4113263
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#84915}
This commit is contained in:
Milad Fa 2022-12-16 17:00:54 -05:00 committed by V8 LUCI CQ
parent f3c984297d
commit b51e75a608
2 changed files with 25 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
src/codegen/ppc/macro-assembler-ppc.cc
View File

@ -3873,6 +3873,30 @@ SIMD_BITMASK_LIST(EMIT_SIMD_BITMASK)
#undef EMIT_SIMD_BITMASK
#undef SIMD_BITMASK_LIST
#define SIMD_QFM_LIST(V) \
V(F64x2Qfma, xvmaddmdp) \
V(F64x2Qfms, xvnmsubmdp) \
V(F32x4Qfma, xvmaddmsp) \
V(F32x4Qfms, xvnmsubmsp)
#define EMIT_SIMD_QFM(name, op) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
Simd128Register src2, Simd128Register src3, \
Simd128Register scratch) { \
Simd128Register dest = dst; \
if (dst != src1) { \
vor(scratch, src1, src1); \
dest = scratch; \
} \
op(dest, src2, src3); \
if (dest != dst) { \
vor(dst, dest, dest); \
} \
}
SIMD_QFM_LIST(EMIT_SIMD_QFM)
#undef EMIT_SIMD_QFM
#undef SIMD_QFM_LIST
void TurboAssembler::I64x2ExtMulLowI32x4S(Simd128Register dst,
Simd128Register src1,
Simd128Register src2,
@ -4514,38 +4538,6 @@ void TurboAssembler::I16x8Q15MulRSatS(Simd128Register dst, Simd128Register src1,
vmhraddshs(dst, src1, src2, scratch);
}
void TurboAssembler::F64x2Qfma(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register src3,
Simd128Register scratch) {
vor(scratch, src2, src2);
xvmaddmdp(scratch, src3, src1);
vor(dst, scratch, scratch);
}
void TurboAssembler::F64x2Qfms(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register src3,
Simd128Register scratch) {
vor(scratch, src2, src2);
xvnmsubmdp(scratch, src3, src1);
vor(dst, scratch, scratch);
}
void TurboAssembler::F32x4Qfma(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register src3,
Simd128Register scratch) {
vor(scratch, src2, src2);
xvmaddmsp(scratch, src3, src1);
vor(dst, scratch, scratch);
}
void TurboAssembler::F32x4Qfms(Simd128Register dst, Simd128Register src1,
Simd128Register src2, Simd128Register src3,
Simd128Register scratch) {
vor(scratch, src2, src2);
xvnmsubmsp(scratch, src3, src1);
vor(dst, scratch, scratch);
}
void TurboAssembler::I8x16Swizzle(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch) {

2
src/codegen/s390/macro-assembler-s390.cc
View File

@ -5685,7 +5685,7 @@ SIMD_ALL_TRUE_LIST(EMIT_SIMD_ALL_TRUE)
#define EMIT_SIMD_QFM(name, op, c1) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
Simd128Register src2, Simd128Register src3) { \
op(dst, src2, src3, src1, Condition(c1), Condition(0)); \
op(dst, src1, src2, src3, Condition(c1), Condition(0)); \
}
SIMD_QFM_LIST(EMIT_SIMD_QFM)
#undef EMIT_SIMD_QFM