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[mips][wasm-simd] Implement v128.andnot

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Port aa12b60  https://crrev.com/c/1980835

Change-Id: Idb82375e3bab94aed2b613d3f32e436fccb4fe53
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2008982
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Auto-Submit: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#65959}
This commit is contained in:
Zhao Jiazhong 2020-01-23 08:12:03 +08:00 committed by Commit Bot
parent 6ef434caf4
commit b6cc74e067
8 changed files with 22 additions and 2 deletions
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7
src/compiler/backend/mips/code-generator-mips.cc
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@ -2306,6 +2306,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMipsS128AndNot: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ nor_v(dst, i.InputSimd128Register(1), i.InputSimd128Register(1));
__ and_v(dst, dst, i.InputSimd128Register(0));
break;
}
case kMipsF32x4Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ bclri_w(i.OutputSimd128Register(), i.InputSimd128Register(0), 31);

1
src/compiler/backend/mips/instruction-codes-mips.h
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@ -261,6 +261,7 @@ namespace compiler {
V(MipsS128Xor) \
V(MipsS128Not) \
V(MipsS128Select) \
V(MipsS128AndNot) \
V(MipsS1x4AnyTrue) \
V(MipsS1x4AllTrue) \
V(MipsS1x8AnyTrue) \

1
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -226,6 +226,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsS128Select:
case kMipsS128Xor:
case kMipsS128Zero:
case kMipsS128AndNot:
case kMipsS16x2Reverse:
case kMipsS16x4Reverse:
case kMipsS16x8InterleaveEven:

3
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2213,7 +2213,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16UConvertI16x8, kMipsI8x16UConvertI16x8) \
V(S128And, kMipsS128And) \
V(S128Or, kMipsS128Or) \
V(S128Xor, kMipsS128Xor)
V(S128Xor, kMipsS128Xor) \
V(S128AndNot, kMipsS128AndNot)
void InstructionSelector::VisitS128Zero(Node* node) {
MipsOperandGenerator g(this);

7
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -2359,6 +2359,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMips64S128AndNot: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ nor_v(dst, i.InputSimd128Register(1), i.InputSimd128Register(1));
__ and_v(dst, dst, i.InputSimd128Register(0));
break;
}
case kMips64F32x4Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ bclri_w(i.OutputSimd128Register(), i.InputSimd128Register(0), 31);

1
src/compiler/backend/mips64/instruction-codes-mips64.h
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@ -291,6 +291,7 @@ namespace compiler {
V(Mips64S128Xor) \
V(Mips64S128Not) \
V(Mips64S128Select) \
V(Mips64S128AndNot) \
V(Mips64S1x4AnyTrue) \
V(Mips64S1x4AllTrue) \
V(Mips64S1x8AnyTrue) \

1
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -248,6 +248,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64S128Or:
case kMips64S128Not:
case kMips64S128Select:
case kMips64S128AndNot:
case kMips64S128Xor:
case kMips64S128Zero:
case kMips64S16x8InterleaveEven:

3
src/compiler/backend/mips64/instruction-selector-mips64.cc
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@ -2867,7 +2867,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16UConvertI16x8, kMips64I8x16UConvertI16x8) \
V(S128And, kMips64S128And) \
V(S128Or, kMips64S128Or) \
V(S128Xor, kMips64S128Xor)
V(S128Xor, kMips64S128Xor) \
V(S128AndNot, kMips64S128AndNot)
void InstructionSelector::VisitS128Zero(Node* node) {
Mips64OperandGenerator g(this);