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[mips64][wasm-simd] Implement I64x2 splat extract_lane replace_lane

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Change-Id: I815979c232f0c781a76dd7954fbba9edabec7359
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2152071
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#67328}
This commit is contained in:
Zhao Jiazhong 2020-04-16 08:56:43 -04:00 committed by Commit Bot
parent 29c1eab92e
commit b9c3921d4f
5 changed files with 32 additions and 2 deletions
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2
src/compiler/backend/instruction-selector.cc
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@ -2612,9 +2612,11 @@ void InstructionSelector::VisitI64x2ReplaceLaneI32Pair(Node* node) {
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_S390X
#if !V8_TARGET_ARCH_ARM64
#if !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI64x2Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2ExtractLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2ReplaceLane(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI64x2Eq(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Ne(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2GtS(Node* node) { UNIMPLEMENTED(); }

21
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -2213,6 +2213,27 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ insert_d(dst, i.InputInt8(1), kScratchReg);
break;
}
case kMips64I64x2Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_d(i.OutputSimd128Register(), i.InputRegister(0));
break;
}
case kMips64I64x2ExtractLane: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ copy_s_d(i.OutputRegister(), i.InputSimd128Register(0),
i.InputInt8(1));
break;
}
case kMips64I64x2ReplaceLane: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ move_v(dst, src);
}
__ insert_d(dst, i.InputInt8(1), i.InputRegister(2));
break;
}
case kMips64I64x2Add: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ addv_d(i.OutputSimd128Register(), i.InputSimd128Register(0),

3
src/compiler/backend/mips64/instruction-codes-mips64.h
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@ -203,6 +203,9 @@ namespace compiler {
V(Mips64F64x2Splat) \
V(Mips64F64x2ExtractLane) \
V(Mips64F64x2ReplaceLane) \
V(Mips64I64x2Splat) \
V(Mips64I64x2ExtractLane) \
V(Mips64I64x2ReplaceLane) \
V(Mips64I64x2Add) \
V(Mips64I64x2Sub) \
V(Mips64I64x2Mul) \

3
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -82,6 +82,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F64x2Ne:
case kMips64F64x2Lt:
case kMips64F64x2Le:
case kMips64I64x2Splat:
case kMips64I64x2ExtractLane:
case kMips64I64x2ReplaceLane:
case kMips64I64x2Add:
case kMips64I64x2Sub:
case kMips64I64x2Mul:

5
src/compiler/backend/mips64/instruction-selector-mips64.cc
View File

@ -2733,7 +2733,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
}
#define SIMD_TYPE_LIST(V) \
V(F64x2) \
V(F32x4) \
V(I64x2) \
V(I32x4) \
V(I16x8) \
V(I8x16)
@ -2883,7 +2885,6 @@ void InstructionSelector::VisitS128Zero(Node* node) {
VisitRR(this, kMips64##Type##Splat, node); \
}
SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
SIMD_VISIT_SPLAT(F64x2)
#undef SIMD_VISIT_SPLAT
#define SIMD_VISIT_EXTRACT_LANE(Type, Sign) \
@ -2892,6 +2893,7 @@ SIMD_VISIT_SPLAT(F64x2)
}
SIMD_VISIT_EXTRACT_LANE(F64x2, )
SIMD_VISIT_EXTRACT_LANE(F32x4, )
SIMD_VISIT_EXTRACT_LANE(I64x2, )
SIMD_VISIT_EXTRACT_LANE(I32x4, )
SIMD_VISIT_EXTRACT_LANE(I16x8, U)
SIMD_VISIT_EXTRACT_LANE(I16x8, S)
@ -2904,7 +2906,6 @@ SIMD_VISIT_EXTRACT_LANE(I8x16, S)
VisitRRIR(this, kMips64##Type##ReplaceLane, node); \
}
SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
SIMD_VISIT_REPLACE_LANE(F64x2)
#undef SIMD_VISIT_REPLACE_LANE
#define SIMD_VISIT_UNOP(Name, instruction) \