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s390: [wasm-simd] Implement simd saturate binary operations

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Change-Id: I847d01568f07da0a73e364a25e3e33e3875f3518
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2061229
Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#66312}
This commit is contained in:
Milad Farazmand 2020-02-18 03:22:22 +00:00 committed by Commit Bot
parent 0fe133cc3e
commit b9e40f7c01
4 changed files with 113 additions and 41 deletions
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96
src/compiler/backend/s390/code-generator-s390.cc
View File

@ -3548,35 +3548,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ op(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0), \
Condition(0), Condition(mode));
case kS390_I32x4SConvertI16x8Low: {
VECTOR_UNPACK(vupl, 1);
VECTOR_UNPACK(vupl, 1)
break;
}
case kS390_I32x4SConvertI16x8High: {
VECTOR_UNPACK(vuph, 1);
VECTOR_UNPACK(vuph, 1)
break;
}
case kS390_I32x4UConvertI16x8Low: {
VECTOR_UNPACK(vupll, 1);
VECTOR_UNPACK(vupll, 1)
break;
}
case kS390_I32x4UConvertI16x8High: {
VECTOR_UNPACK(vuplh, 1);
VECTOR_UNPACK(vuplh, 1)
break;
}
case kS390_I16x8SConvertI8x16Low: {
VECTOR_UNPACK(vupl, 0);
VECTOR_UNPACK(vupl, 0)
break;
}
case kS390_I16x8SConvertI8x16High: {
VECTOR_UNPACK(vuph, 0);
VECTOR_UNPACK(vuph, 0)
break;
}
case kS390_I16x8UConvertI8x16Low: {
VECTOR_UNPACK(vupll, 0);
VECTOR_UNPACK(vupll, 0)
break;
}
case kS390_I16x8UConvertI8x16High: {
VECTOR_UNPACK(vuplh, 0);
VECTOR_UNPACK(vuplh, 0)
break;
}
#undef VECTOR_UNPACK
@ -3609,6 +3609,86 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
#undef VECTOR_PACK_UNSIGNED
#define BINOP_EXTRACT(op, extract_high, extract_low, mode) \
Simd128Register src1 = i.InputSimd128Register(0); \
Simd128Register src2 = i.InputSimd128Register(1); \
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); \
Simd128Register tempFPReg2 = i.ToSimd128Register(instr->TempAt(1)); \
__ extract_high(kScratchDoubleReg, src1, Condition(0), Condition(0), \
Condition(mode)); \
__ extract_high(tempFPReg1, src2, Condition(0), Condition(0), \
Condition(mode)); \
__ op(kScratchDoubleReg, kScratchDoubleReg, tempFPReg1, Condition(0), \
Condition(0), Condition(mode + 1)); \
__ extract_low(tempFPReg1, src1, Condition(0), Condition(0), \
Condition(mode)); \
__ extract_low(tempFPReg2, src2, Condition(0), Condition(0), \
Condition(mode)); \
__ op(tempFPReg1, tempFPReg1, tempFPReg2, Condition(0), Condition(0), \
Condition(mode + 1));
case kS390_I16x8AddSaturateS: {
BINOP_EXTRACT(va, vuph, vupl, 1)
__ vpks(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(2));
break;
}
case kS390_I16x8SubSaturateS: {
BINOP_EXTRACT(vs, vuph, vupl, 1)
__ vpks(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(2));
break;
}
case kS390_I16x8AddSaturateU: {
BINOP_EXTRACT(va, vuplh, vupll, 1)
__ vpkls(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(2));
break;
}
case kS390_I16x8SubSaturateU: {
BINOP_EXTRACT(vs, vuplh, vupll, 1)
// negative to 0
__ vx(tempFPReg2, tempFPReg2, tempFPReg2, Condition(0), Condition(0),
Condition(0));
__ vmx(kScratchDoubleReg, tempFPReg2, kScratchDoubleReg, Condition(0),
Condition(0), Condition(2));
__ vmx(tempFPReg1, tempFPReg2, tempFPReg1, Condition(0), Condition(0),
Condition(2));
__ vpkls(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(2));
break;
}
case kS390_I8x16AddSaturateS: {
BINOP_EXTRACT(va, vuph, vupl, 0)
__ vpks(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(1));
break;
}
case kS390_I8x16SubSaturateS: {
BINOP_EXTRACT(vs, vuph, vupl, 0)
__ vpks(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(1));
break;
}
case kS390_I8x16AddSaturateU: {
BINOP_EXTRACT(va, vuplh, vupll, 0)
__ vpkls(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(1));
break;
}
case kS390_I8x16SubSaturateU: {
BINOP_EXTRACT(vs, vuplh, vupll, 0)
// negative to 0
__ vx(tempFPReg2, tempFPReg2, tempFPReg2, Condition(0), Condition(0),
Condition(0));
__ vmx(kScratchDoubleReg, tempFPReg2, kScratchDoubleReg, Condition(0),
Condition(0), Condition(1));
__ vmx(tempFPReg1, tempFPReg2, tempFPReg1, Condition(0), Condition(0),
Condition(1));
__ vpkls(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(1));
break;
}
#undef BINOP_EXTRACT
default:
UNREACHABLE();
}

10
src/compiler/backend/s390/instruction-codes-s390.h
View File

@ -232,7 +232,6 @@ namespace compiler {
V(S390_I32x4GtU) \
V(S390_I32x4GeU) \
V(S390_I32x4Neg) \
V(S390_I16x8Splat) \
V(S390_I32x4Shl) \
V(S390_I32x4ShrS) \
V(S390_I32x4ShrU) \
@ -242,6 +241,7 @@ namespace compiler {
V(S390_I32x4SConvertI16x8High) \
V(S390_I32x4UConvertI16x8Low) \
V(S390_I32x4UConvertI16x8High) \
V(S390_I16x8Splat) \
V(S390_I16x8ExtractLaneU) \
V(S390_I16x8ExtractLaneS) \
V(S390_I16x8ReplaceLane) \
@ -269,6 +269,10 @@ namespace compiler {
V(S390_I16x8SConvertI8x16High) \
V(S390_I16x8UConvertI8x16Low) \
V(S390_I16x8UConvertI8x16High) \
V(S390_I16x8AddSaturateS) \
V(S390_I16x8SubSaturateS) \
V(S390_I16x8AddSaturateU) \
V(S390_I16x8SubSaturateU) \
V(S390_I8x16Splat) \
V(S390_I8x16ExtractLaneU) \
V(S390_I8x16ExtractLaneS) \
@ -292,6 +296,10 @@ namespace compiler {
V(S390_I8x16Neg) \
V(S390_I8x16SConvertI16x8) \
V(S390_I8x16UConvertI16x8) \
V(S390_I8x16AddSaturateS) \
V(S390_I8x16SubSaturateS) \
V(S390_I8x16AddSaturateU) \
V(S390_I8x16SubSaturateU) \
V(S390_S1x4AnyTrue) \
V(S390_S1x8AnyTrue) \
V(S390_S1x16AnyTrue) \

8
src/compiler/backend/s390/instruction-scheduler-s390.cc
View File

@ -215,6 +215,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I16x8SConvertI8x16High:
case kS390_I16x8UConvertI8x16Low:
case kS390_I16x8UConvertI8x16High:
case kS390_I16x8AddSaturateS:
case kS390_I16x8SubSaturateS:
case kS390_I16x8AddSaturateU:
case kS390_I16x8SubSaturateU:
case kS390_I8x16Splat:
case kS390_I8x16ExtractLaneU:
case kS390_I8x16ExtractLaneS:
@ -238,6 +242,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_I8x16Neg:
case kS390_I8x16SConvertI16x8:
case kS390_I8x16UConvertI16x8:
case kS390_I8x16AddSaturateS:
case kS390_I8x16SubSaturateS:
case kS390_I8x16AddSaturateU:
case kS390_I8x16SubSaturateU:
case kS390_S1x4AnyTrue:
case kS390_S1x8AnyTrue:
case kS390_S1x16AnyTrue:

40
src/compiler/backend/s390/instruction-selector-s390.cc
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@ -2556,6 +2556,10 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I16x8GeU) \
V(I16x8SConvertI32x4) \
V(I16x8UConvertI32x4) \
V(I16x8AddSaturateS) \
V(I16x8SubSaturateS) \
V(I16x8AddSaturateU) \
V(I16x8SubSaturateU) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16Mul) \
@ -2571,6 +2575,10 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
V(I8x16GeU) \
V(I8x16SConvertI16x8) \
V(I8x16UConvertI16x8) \
V(I8x16AddSaturateS) \
V(I8x16SubSaturateS) \
V(I8x16AddSaturateU) \
V(I8x16SubSaturateU) \
V(S128And) \
V(S128Or) \
V(S128Xor)
@ -2722,22 +2730,6 @@ void InstructionSelector::VisitS128Select(Node* node) {
g.UseRegister(node->InputAt(2)));
}
void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) {
UNIMPLEMENTED();
}
@ -2746,22 +2738,6 @@ void InstructionSelector::VisitI8x16RoundingAverageU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16SubSaturateS(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16AddSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI8x16SubSaturateU(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::EmitPrepareResults(