AuroraMiddleware/v8
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Move them from .data to .rodata.

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R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/659663005

Patch from Ben Noordhuis <ben@strongloop.com>.

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24672 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
bmeurer@chromium.org 2014-10-17 04:03:15 +00:00
parent f3bfd04bcf
commit bacde72e20
4 changed files with 9 additions and 9 deletions
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2
src/arm/disasm-arm.cc
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@ -148,7 +148,7 @@ void Decoder::Print(const char* str) {
// These condition names are defined in a way to match the native disassembler
// formatting. See for example the command "objdump -d <binary file>".
static const char* cond_names[kNumberOfConditions] = {
static const char* const cond_names[kNumberOfConditions] = {
"eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
"hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
};

2
src/arm64/disasm-arm64.cc
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@ -1695,7 +1695,7 @@ int Disassembler::SubstituteBarrierField(Instruction* instr,
DCHECK(format[0] == 'M');
USE(format);
static const char* options[4][4] = {
static const char* const options[4][4] = {
{ "sy (0b0000)", "oshld", "oshst", "osh" },
{ "sy (0b0100)", "nshld", "nshst", "nsh" },
{ "sy (0b1000)", "ishld", "ishst", "ish" },

6
src/ia32/disasm-ia32.cc
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@ -1690,17 +1690,17 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
//------------------------------------------------------------------------------
static const char* cpu_regs[8] = {
static const char* const cpu_regs[8] = {
"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"
};
static const char* byte_cpu_regs[8] = {
static const char* const byte_cpu_regs[8] = {
"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
};
static const char* xmm_regs[8] = {
static const char* const xmm_regs[8] = {
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"
};

8
src/x64/disasm-x64.cc
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@ -252,7 +252,7 @@ static v8::base::LazyInstance<InstructionTable>::type instruction_table =
LAZY_INSTANCE_INITIALIZER;
static InstructionDesc cmov_instructions[16] = {
static const InstructionDesc cmov_instructions[16] = {
{"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
{"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
{"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
@ -1808,19 +1808,19 @@ int DisassemblerX64::InstructionDecode(v8::internal::Vector<char> out_buffer,
//------------------------------------------------------------------------------
static const char* cpu_regs[16] = {
static const char* const cpu_regs[16] = {
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
};
static const char* byte_cpu_regs[16] = {
static const char* const byte_cpu_regs[16] = {
"al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
"r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"
};
static const char* xmm_regs[16] = {
static const char* const xmm_regs[16] = {
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
"xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
};