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[riscv64] Add a flag for simulator debug and rename riscv flag

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Change-Id: I89ceb023d109f3ad69c0d679135c52cd278b4af3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2878150
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#74494}
This commit is contained in:
Lu Yahan 2021-05-11 09:49:14 +08:00 committed by V8 LUCI CQ
parent cf35926aff
commit bb01d957ba
4 changed files with 12 additions and 7 deletions
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2
src/codegen/riscv64/assembler-riscv64.h
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@ -53,7 +53,7 @@ namespace v8 {
namespace internal {
#define DEBUG_PRINTF(...) \
if (FLAG_debug_riscv) { \
if (FLAG_riscv_debug) { \
printf(__VA_ARGS__); \
}

4
src/codegen/riscv64/macro-assembler-riscv64.cc
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@ -1486,7 +1486,7 @@ void TurboAssembler::li(Register rd, Operand j, LiFlags mode) {
UseScratchRegisterScope temps(this);
int count = li_estimate(j.immediate(), temps.hasAvailable());
int reverse_count = li_estimate(~j.immediate(), temps.hasAvailable());
if (!FLAG_disable_riscv_constant_pool && count >= 4 && reverse_count >= 4) {
if (FLAG_riscv_constant_pool && count >= 4 && reverse_count >= 4) {
// Ld a Address from a constant pool.
RecordEntry((uint64_t)j.immediate(), j.rmode());
auipc(rd, 0);
@ -3857,7 +3857,7 @@ void MacroAssembler::JumpToExternalReference(const ExternalReference& builtin,
void MacroAssembler::JumpToInstructionStream(Address entry) {
// Ld a Address from a constant pool.
// Record a value into constant pool.
if (FLAG_disable_riscv_constant_pool) {
if (!FLAG_riscv_constant_pool) {
li(kOffHeapTrampolineRegister, Operand(entry, RelocInfo::OFF_HEAP_TARGET));
} else {
RecordEntry(entry, RelocInfo::OFF_HEAP_TARGET);

2
src/execution/riscv64/simulator-riscv64.cc
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@ -1105,7 +1105,7 @@ int64_t Simulator::get_pc() const { return registers_[pc]; }
// TODO(plind): refactor this messy debug code when we do unaligned access.
void Simulator::DieOrDebug() {
if ((1)) { // Flag for this was removed.
if (FLAG_riscv_trap_to_simulator_debugger) {
RiscvDebugger dbg(this);
dbg.Debug();
} else {

11
src/flags/flag-definitions.h
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@ -1320,10 +1320,15 @@ DEFINE_BOOL(partial_constant_pool, true,
DEFINE_STRING(sim_arm64_optional_features, "none",
"enable optional features on the simulator for testing: none or "
"all")
DEFINE_BOOL(debug_riscv, false, "enable debug prints")
DEFINE_BOOL(disable_riscv_constant_pool, false,
"disable constant pool (RISCV only)")
#if defined(V8_TARGET_ARCH_RISCV64)
DEFINE_BOOL(riscv_trap_to_simulator_debugger, false,
"enable simulator trap to debugger")
DEFINE_BOOL(riscv_debug, false, "enable debug prints")
DEFINE_BOOL(riscv_constant_pool, true,
"enable constant pool (RISCV only)")
#endif
// Controlling source positions for Torque/CSA code.
DEFINE_BOOL(enable_source_at_csa_bind, false,