From bb09b6acd58eedcff3117f1b0a0efc4f764756ab Mon Sep 17 00:00:00 2001 From: Zhao Jiazhong Date: Fri, 16 Oct 2020 13:53:01 +0800 Subject: [PATCH] [mips][wasm-simd] Implement I32x4DotI16x8S Change-Id: Ie187d6ec848414d725b18b9a20be3c65f94f86ba Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2477752 Reviewed-by: Zhi An Ng Commit-Queue: Zhao Jiazhong Cr-Commit-Position: refs/heads/master@{#70580} --- src/compiler/backend/mips/code-generator-mips.cc | 6 ++++++ src/compiler/backend/mips/instruction-codes-mips.h | 1 + src/compiler/backend/mips/instruction-scheduler-mips.cc | 1 + src/compiler/backend/mips/instruction-selector-mips.cc | 1 + src/compiler/backend/mips64/code-generator-mips64.cc | 6 ++++++ src/compiler/backend/mips64/instruction-codes-mips64.h | 1 + src/compiler/backend/mips64/instruction-scheduler-mips64.cc | 1 + src/compiler/backend/mips64/instruction-selector-mips64.cc | 1 + 8 files changed, 18 insertions(+) diff --git a/src/compiler/backend/mips/code-generator-mips.cc b/src/compiler/backend/mips/code-generator-mips.cc index a57cf408cd..56b7c3b882 100644 --- a/src/compiler/backend/mips/code-generator-mips.cc +++ b/src/compiler/backend/mips/code-generator-mips.cc @@ -2585,6 +2585,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( __ copy_u_b(dst, scratch0, 0); break; } + case kMipsI32x4DotI16x8S: { + CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); + __ dotp_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } case kMipsI16x8Splat: { CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); __ fill_h(i.OutputSimd128Register(), i.InputRegister(0)); diff --git a/src/compiler/backend/mips/instruction-codes-mips.h b/src/compiler/backend/mips/instruction-codes-mips.h index 06a2e5d0d1..47d439af58 100644 --- a/src/compiler/backend/mips/instruction-codes-mips.h +++ b/src/compiler/backend/mips/instruction-codes-mips.h @@ -217,6 +217,7 @@ namespace compiler { V(MipsI32x4GeU) \ V(MipsI32x4Abs) \ V(MipsI32x4BitMask) \ + V(MipsI32x4DotI16x8S) \ V(MipsI16x8Splat) \ V(MipsI16x8ExtractLaneU) \ V(MipsI16x8ExtractLaneS) \ diff --git a/src/compiler/backend/mips/instruction-scheduler-mips.cc b/src/compiler/backend/mips/instruction-scheduler-mips.cc index 54e5fca6c7..bf28eec443 100644 --- a/src/compiler/backend/mips/instruction-scheduler-mips.cc +++ b/src/compiler/backend/mips/instruction-scheduler-mips.cc @@ -180,6 +180,7 @@ int InstructionScheduler::GetTargetInstructionFlags( case kMipsI32x4UConvertI16x8Low: case kMipsI32x4Abs: case kMipsI32x4BitMask: + case kMipsI32x4DotI16x8S: case kMipsI8x16Add: case kMipsI8x16AddSatS: case kMipsI8x16AddSatU: diff --git a/src/compiler/backend/mips/instruction-selector-mips.cc b/src/compiler/backend/mips/instruction-selector-mips.cc index 35348244ec..21749ce2a9 100644 --- a/src/compiler/backend/mips/instruction-selector-mips.cc +++ b/src/compiler/backend/mips/instruction-selector-mips.cc @@ -2191,6 +2191,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { V(I32x4GeU, kMipsI32x4GeU) \ V(I32x4Abs, kMipsI32x4Abs) \ V(I32x4BitMask, kMipsI32x4BitMask) \ + V(I32x4DotI16x8S, kMipsI32x4DotI16x8S) \ V(I16x8Add, kMipsI16x8Add) \ V(I16x8AddSatS, kMipsI16x8AddSatS) \ V(I16x8AddSatU, kMipsI16x8AddSatU) \ diff --git a/src/compiler/backend/mips64/code-generator-mips64.cc b/src/compiler/backend/mips64/code-generator-mips64.cc index 5e8377a99f..4ba156e119 100644 --- a/src/compiler/backend/mips64/code-generator-mips64.cc +++ b/src/compiler/backend/mips64/code-generator-mips64.cc @@ -2763,6 +2763,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( __ copy_u_b(dst, scratch0, 0); break; } + case kMips64I32x4DotI16x8S: { + CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); + __ dotp_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0), + i.InputSimd128Register(1)); + break; + } case kMips64I16x8Splat: { CpuFeatureScope msa_scope(tasm(), MIPS_SIMD); __ fill_h(i.OutputSimd128Register(), i.InputRegister(0)); diff --git a/src/compiler/backend/mips64/instruction-codes-mips64.h b/src/compiler/backend/mips64/instruction-codes-mips64.h index 057ff4dd4e..10a974c827 100644 --- a/src/compiler/backend/mips64/instruction-codes-mips64.h +++ b/src/compiler/backend/mips64/instruction-codes-mips64.h @@ -252,6 +252,7 @@ namespace compiler { V(Mips64I32x4GeU) \ V(Mips64I32x4Abs) \ V(Mips64I32x4BitMask) \ + V(Mips64I32x4DotI16x8S) \ V(Mips64I16x8Splat) \ V(Mips64I16x8ExtractLaneU) \ V(Mips64I16x8ExtractLaneS) \ diff --git a/src/compiler/backend/mips64/instruction-scheduler-mips64.cc b/src/compiler/backend/mips64/instruction-scheduler-mips64.cc index 7299343810..bbab3c4b88 100644 --- a/src/compiler/backend/mips64/instruction-scheduler-mips64.cc +++ b/src/compiler/backend/mips64/instruction-scheduler-mips64.cc @@ -213,6 +213,7 @@ int InstructionScheduler::GetTargetInstructionFlags( case kMips64I32x4UConvertI16x8Low: case kMips64I32x4Abs: case kMips64I32x4BitMask: + case kMips64I32x4DotI16x8S: case kMips64I8x16Add: case kMips64I8x16AddSatS: case kMips64I8x16AddSatU: diff --git a/src/compiler/backend/mips64/instruction-selector-mips64.cc b/src/compiler/backend/mips64/instruction-selector-mips64.cc index 5cc2e939e4..068a8410f5 100644 --- a/src/compiler/backend/mips64/instruction-selector-mips64.cc +++ b/src/compiler/backend/mips64/instruction-selector-mips64.cc @@ -2871,6 +2871,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { V(I32x4GeS, kMips64I32x4GeS) \ V(I32x4GtU, kMips64I32x4GtU) \ V(I32x4GeU, kMips64I32x4GeU) \ + V(I32x4DotI16x8S, kMips64I32x4DotI16x8S) \ V(I16x8Add, kMips64I16x8Add) \ V(I16x8AddSatS, kMips64I16x8AddSatS) \ V(I16x8AddSatU, kMips64I16x8AddSatU) \