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MIPS: Cleaned up CpuFeature scope handling.

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Port r13823 (cb37ab63)

BUG=

Review URL: https://codereview.chromium.org/12424004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13876 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
palfia@homejinni.com 2013-03-08 00:54:19 +00:00
parent 4c91b74232
commit bb380cf971
2 changed files with 8 additions and 8 deletions
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2
src/mips/stub-cache-mips.cc
View File

@ -3520,7 +3520,7 @@ void KeyedStoreStubCompiler::GenerateStoreExternalArray(
f0, t2, t3, // These are: double_dst, dst_mantissa, dst_exponent.
t0, f2); // These are: scratch2, single_scratch.
if (destination == FloatingPointHelper::kFPURegisters) {
CpuFeatureScope scope(masm(), FPU);
CpuFeatureScope scope(masm, FPU);
__ sdc1(f0, MemOperand(a3, 0));
} else {
__ sw(t2, MemOperand(a3, 0));

14
test/cctest/test-assembler-mips.cc
View File

@ -287,7 +287,7 @@ TEST(MIPS3) {
Label L, C;
if (CpuFeatures::IsSupported(FPU)) {
CpuFeatures::Scope scope(FPU);
CpuFeatureScope scope(&assm, FPU);
__ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
__ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
@ -370,7 +370,7 @@ TEST(MIPS4) {
Label L, C;
if (CpuFeatures::IsSupported(FPU)) {
CpuFeatures::Scope scope(FPU);
CpuFeatureScope scope(&assm, FPU);
__ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
__ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
@ -431,7 +431,7 @@ TEST(MIPS5) {
Label L, C;
if (CpuFeatures::IsSupported(FPU)) {
CpuFeatures::Scope scope(FPU);
CpuFeatureScope scope(&assm, FPU);
// Load all structure elements to registers.
__ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
@ -579,7 +579,7 @@ TEST(MIPS7) {
Label neither_is_nan, less_than, outa_here;
if (CpuFeatures::IsSupported(FPU)) {
CpuFeatures::Scope scope(FPU);
CpuFeatureScope scope(&assm, FPU);
__ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
__ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
@ -792,7 +792,7 @@ TEST(MIPS10) {
Label L, C;
if (CpuFeatures::IsSupported(FPU) && kArchVariant == kMips32r2) {
CpuFeatures::Scope scope(FPU);
CpuFeatureScope scope(&assm, FPU);
// Load all structure elements to registers.
__ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
@ -1097,7 +1097,7 @@ TEST(MIPS13) {
MacroAssembler assm(Isolate::Current(), NULL, 0);
if (CpuFeatures::IsSupported(FPU)) {
CpuFeatures::Scope scope(FPU);
CpuFeatureScope scope(&assm, FPU);
__ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_small_in)));
__ Cvt_d_uw(f10, t0, f22);
@ -1180,7 +1180,7 @@ TEST(MIPS14) {
MacroAssembler assm(Isolate::Current(), NULL, 0);
if (CpuFeatures::IsSupported(FPU)) {
CpuFeatures::Scope scope(FPU);
CpuFeatureScope scope(&assm, FPU);
// Save FCSR.
__ cfc1(a1, FCSR);