PPC: Add and use mtrcrf to clear the condition register

Condition register might need to be cleared before
running instructions to assure sticky bits are cleared.

Change-Id: Id18e5759e4cc9f03c2e9334f41b5ff179639ad22
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2562747
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71460}
This commit is contained in:
Milad Fa 2020-11-27 11:53:25 -05:00 committed by Commit Bot
parent 064ee3c835
commit bba4817bf0
3 changed files with 8 additions and 2 deletions

View File

@ -1466,6 +1466,9 @@ void Assembler::mcrfs(CRegister cr, FPSCRBit bit) {
void Assembler::mfcr(Register dst) { emit(EXT2 | MFCR | dst.code() * B21); }
void Assembler::mtcrf(unsigned char FXM, Register src) {
emit(MTCRF | src.code() * B21 | FXM * B12);
}
#if V8_TARGET_ARCH_PPC64
void Assembler::mffprd(Register dst, DoubleRegister src) {
emit(EXT2 | MFVSRD | src.code() * B21 | dst.code() * B16);

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@ -922,6 +922,7 @@ class Assembler : public AssemblerBase {
void mtxer(Register src);
void mcrfs(CRegister cr, FPSCRBit bit);
void mfcr(Register dst);
void mtcrf(unsigned char FXM, Register src);
#if V8_TARGET_ARCH_PPC64
void mffprd(Register dst, DoubleRegister src);
void mffprwz(Register dst, DoubleRegister src);

View File

@ -3049,9 +3049,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Register dst = i.OutputRegister();
constexpr int bit_number = 24;
__ li(r0, Operand(0));
__ li(ip, Operand(-1));
__ li(ip, Operand(1));
// Check if both lanes are 0, if so then return false.
__ vxor(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
__ mtcrf(0xFF, r0); // Clear cr.
__ vcmpequd(kScratchDoubleReg, src, kScratchDoubleReg, SetRC);
__ isel(dst, r0, ip, bit_number);
break;
@ -3061,9 +3062,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Register dst = i.OutputRegister(); \
constexpr int bit_number = 24; \
__ li(r0, Operand(0)); \
__ li(ip, Operand(-1)); \
__ li(ip, Operand(1)); \
/* Check if all lanes > 0, if not then return false.*/ \
__ vxor(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); \
__ mtcrf(0xFF, r0); /* Clear cr.*/ \
__ opcode(kScratchDoubleReg, src, kScratchDoubleReg, SetRC); \
__ isel(dst, ip, r0, bit_number);
case kPPC_V64x2AllTrue: {