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[mips][wasm-simd] Merge all any_true to v128.any_true

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Port: 6d3a53e7f2

Bug: v8:11331

Change-Id: I6aaba8e4d25e01121f0f7e01f67af3b5c7202ba6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2666712
Auto-Submit: Liu yu <liuyu@loongson.cn>
Reviewed-by: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#72470}
This commit is contained in:
LiuYu 2021-02-02 10:24:44 +08:00 committed by Commit Bot
parent fb0f95bcbf
commit bc70b6e475
10 changed files with 17 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/compiler/backend/mips/code-generator-mips.cc
View File

@ -3048,9 +3048,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMipsV32x4AnyTrue:
case kMipsV16x8AnyTrue:
case kMipsV8x16AnyTrue: {
case kMipsV128AnyTrue: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Register dst = i.OutputRegister();
Label all_false;

4
src/compiler/backend/mips/instruction-codes-mips.h
View File

@ -299,12 +299,10 @@ namespace compiler {
V(MipsS128Not) \
V(MipsS128Select) \
V(MipsS128AndNot) \
V(MipsV32x4AnyTrue) \
V(MipsV32x4AllTrue) \
V(MipsV16x8AnyTrue) \
V(MipsV16x8AllTrue) \
V(MipsV8x16AnyTrue) \
V(MipsV8x16AllTrue) \
V(MipsV128AnyTrue) \
V(MipsS32x4InterleaveRight) \
V(MipsS32x4InterleaveLeft) \
V(MipsS32x4PackEven) \

6
src/compiler/backend/mips/instruction-scheduler-mips.cc
View File

@ -273,12 +273,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsS16x8InterleaveRight:
case kMipsS16x8PackEven:
case kMipsS16x8PackOdd:
case kMipsV8x16AllTrue:
case kMipsV8x16AnyTrue:
case kMipsV32x4AllTrue:
case kMipsV32x4AnyTrue:
case kMipsV16x8AllTrue:
case kMipsV16x8AnyTrue:
case kMipsV8x16AllTrue:
case kMipsV128AnyTrue:
case kMipsS32x4InterleaveEven:
case kMipsS32x4InterleaveLeft:
case kMipsS32x4InterleaveOdd:

6
src/compiler/backend/mips/instruction-selector-mips.cc
View File

@ -2153,12 +2153,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16Neg, kMipsI8x16Neg) \
V(I8x16BitMask, kMipsI8x16BitMask) \
V(S128Not, kMipsS128Not) \
V(V32x4AnyTrue, kMipsV32x4AnyTrue) \
V(V32x4AllTrue, kMipsV32x4AllTrue) \
V(V16x8AnyTrue, kMipsV16x8AnyTrue) \
V(V16x8AllTrue, kMipsV16x8AllTrue) \
V(V8x16AnyTrue, kMipsV8x16AnyTrue) \
V(V8x16AllTrue, kMipsV8x16AllTrue)
V(V8x16AllTrue, kMipsV8x16AllTrue) \
V(V128AnyTrue, kMipsV128AnyTrue)
#define SIMD_SHIFT_OP_LIST(V) \
V(I64x2Shl) \

4
src/compiler/backend/mips64/code-generator-mips64.cc
View File

@ -3248,9 +3248,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMips64V32x4AnyTrue:
case kMips64V16x8AnyTrue:
case kMips64V8x16AnyTrue: {
case kMips64V128AnyTrue: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Register dst = i.OutputRegister();
Label all_false;

4
src/compiler/backend/mips64/instruction-codes-mips64.h
View File

@ -324,12 +324,10 @@ namespace compiler {
V(Mips64S128Not) \
V(Mips64S128Select) \
V(Mips64S128AndNot) \
V(Mips64V32x4AnyTrue) \
V(Mips64V32x4AllTrue) \
V(Mips64V16x8AnyTrue) \
V(Mips64V16x8AllTrue) \
V(Mips64V8x16AnyTrue) \
V(Mips64V8x16AllTrue) \
V(Mips64V128AnyTrue) \
V(Mips64S32x4InterleaveRight) \
V(Mips64S32x4InterleaveLeft) \
V(Mips64S32x4PackEven) \

6
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
View File

@ -292,12 +292,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64S16x8PackOdd:
case kMips64S16x2Reverse:
case kMips64S16x4Reverse:
case kMips64V8x16AllTrue:
case kMips64V8x16AnyTrue:
case kMips64V32x4AllTrue:
case kMips64V32x4AnyTrue:
case kMips64V16x8AllTrue:
case kMips64V16x8AnyTrue:
case kMips64V8x16AllTrue:
case kMips64V128AnyTrue:
case kMips64S32x4InterleaveEven:
case kMips64S32x4InterleaveOdd:
case kMips64S32x4InterleaveLeft:

6
src/compiler/backend/mips64/instruction-selector-mips64.cc
View File

@ -2891,12 +2891,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16Abs, kMips64I8x16Abs) \
V(I8x16BitMask, kMips64I8x16BitMask) \
V(S128Not, kMips64S128Not) \
V(V32x4AnyTrue, kMips64V32x4AnyTrue) \
V(V32x4AllTrue, kMips64V32x4AllTrue) \
V(V16x8AnyTrue, kMips64V16x8AnyTrue) \
V(V16x8AllTrue, kMips64V16x8AllTrue) \
V(V8x16AnyTrue, kMips64V8x16AnyTrue) \
V(V8x16AllTrue, kMips64V8x16AllTrue)
V(V8x16AllTrue, kMips64V8x16AllTrue) \
V(V128AnyTrue, kMips64V128AnyTrue)
#define SIMD_SHIFT_OP_LIST(V) \
V(I64x2Shl) \

16
src/wasm/baseline/mips/liftoff-assembler-mips.h
View File

@ -1987,9 +1987,9 @@ void LiftoffAssembler::emit_i8x16_neg(LiftoffRegister dst,
bailout(kSimd, "emit_i8x16_neg");
}
void LiftoffAssembler::emit_v8x16_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "emit_v8x16_anytrue");
void LiftoffAssembler::emit_v128_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "emit_v128_anytrue");
}
void LiftoffAssembler::emit_v8x16_alltrue(LiftoffRegister dst,
@ -2102,11 +2102,6 @@ void LiftoffAssembler::emit_i16x8_neg(LiftoffRegister dst,
bailout(kSimd, "emit_i16x8_neg");
}
void LiftoffAssembler::emit_v16x8_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "emit_v16x8_anytrue");
}
void LiftoffAssembler::emit_v16x8_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "emit_v16x8_alltrue");
@ -2217,11 +2212,6 @@ void LiftoffAssembler::emit_i32x4_neg(LiftoffRegister dst,
bailout(kSimd, "emit_i32x4_neg");
}
void LiftoffAssembler::emit_v32x4_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "emit_v32x4_anytrue");
}
void LiftoffAssembler::emit_v32x4_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "emit_v32x4_alltrue");

14
src/wasm/baseline/mips64/liftoff-assembler-mips64.h
View File

@ -1939,8 +1939,8 @@ void LiftoffAssembler::emit_i8x16_neg(LiftoffRegister dst,
subv_b(dst.fp().toW(), kSimd128RegZero, src.fp().toW());
}
void LiftoffAssembler::emit_v8x16_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
void LiftoffAssembler::emit_v128_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
liftoff::EmitAnyTrue(this, dst, src);
}
@ -2069,11 +2069,6 @@ void LiftoffAssembler::emit_i16x8_neg(LiftoffRegister dst,
subv_h(dst.fp().toW(), kSimd128RegZero, src.fp().toW());
}
void LiftoffAssembler::emit_v16x8_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
liftoff::EmitAnyTrue(this, dst, src);
}
void LiftoffAssembler::emit_v16x8_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
liftoff::EmitAllTrue(this, dst, src, MSA_BRANCH_H);
@ -2198,11 +2193,6 @@ void LiftoffAssembler::emit_i32x4_neg(LiftoffRegister dst,
subv_w(dst.fp().toW(), kSimd128RegZero, src.fp().toW());
}
void LiftoffAssembler::emit_v32x4_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
liftoff::EmitAnyTrue(this, dst, src);
}
void LiftoffAssembler::emit_v32x4_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
liftoff::EmitAllTrue(this, dst, src, MSA_BRANCH_W);