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[wasm][simd] Align printed instructions/types with spec

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The spec uses "v128" (not "s128") as the vector type name.
Some conversion instructions have more specific names that we used to
print, e.g. "i32x4.trunc_sat_f32x4_s" instead of "...convert...".

Bug: v8:8460
Change-Id: I4e06f452de6ce8b06670a8c5e53142c36d5e6010
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3704497
Commit-Queue: Andreas Haas <ahaas@chromium.org>
Auto-Submit: Jakob Kummerow <jkummerow@chromium.org>
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Cr-Commit-Position: refs/heads/main@{#81274}
This commit is contained in:
Jakob Kummerow 2022-06-20 15:29:34 +02:00 committed by V8 LUCI CQ
parent 8f855e977a
commit bdb6322cc2
3 changed files with 274 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/wasm/value-type.h
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@ -37,7 +37,7 @@ class Simd128;
V(I64, 3, I64, Int64, 'l', "i64") \
V(F32, 2, F32, Float32, 'f', "f32") \
V(F64, 3, F64, Float64, 'd', "f64") \
V(S128, 4, S128, Simd128, 's', "s128") \
V(S128, 4, S128, Simd128, 's', "v128") \
V(I8, 0, I8, Int8, 'b', "i8") \
V(I16, 1, I16, Int16, 'h', "i16")

49
src/wasm/wasm-opcodes-inl.h
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@ -35,40 +35,43 @@ namespace wasm {
#define CASE_I32x4_OP(name, str) CASE_OP(I32x4##name, "i32x4." str)
#define CASE_I16x8_OP(name, str) CASE_OP(I16x8##name, "i16x8." str)
#define CASE_I8x16_OP(name, str) CASE_OP(I8x16##name, "i8x16." str)
#define CASE_S128_OP(name, str) CASE_OP(S128##name, "s128." str)
#define CASE_S128_OP(name, str) CASE_OP(S128##name, "v128." str)
#define CASE_V128_OP(name, str) CASE_OP(V128##name, "v128." str)
#define CASE_S64x2_OP(name, str) CASE_OP(S64x2##name, "s64x2." str)
#define CASE_S32x4_OP(name, str) CASE_OP(S32x4##name, "s32x4." str)
#define CASE_S16x8_OP(name, str) CASE_OP(S16x8##name, "s16x8." str)
#define CASE_V64x2_OP(name, str) CASE_OP(V64x2##name, "v64x2." str)
#define CASE_V32x4_OP(name, str) CASE_OP(V32x4##name, "v32x4." str)
#define CASE_V16x8_OP(name, str) CASE_OP(V16x8##name, "v16x8." str)
#define CASE_V8x16_OP(name, str) CASE_OP(V8x16##name, "v8x16." str)
#define CASE_INT_OP(name, str) CASE_I32_OP(name, str) CASE_I64_OP(name, str)
#define CASE_FLOAT_OP(name, str) CASE_F32_OP(name, str) CASE_F64_OP(name, str)
#define CASE_ALL_OP(name, str) CASE_FLOAT_OP(name, str) CASE_INT_OP(name, str)
#define CASE_SIMD_OP(name, str) \
CASE_F64x2_OP(name, str) CASE_I64x2_OP(name, str) CASE_F32x4_OP(name, str) \
CASE_I32x4_OP(name, str) CASE_I16x8_OP(name, str) \
CASE_I8x16_OP(name, str)
#define CASE_SIMDF_OP(name, str) \
CASE_F32x4_OP(name, str) CASE_F64x2_OP(name, str)
#define CASE_SIMDI_OP(name, str) \
CASE_I64x2_OP(name, str) CASE_I32x4_OP(name, str) CASE_I16x8_OP(name, str) \
CASE_I8x16_OP(name, str)
#define CASE_SIMDI_NO64X2_OP(name, str) \
CASE_I32x4_OP(name, str) CASE_I16x8_OP(name, str) CASE_I8x16_OP(name, str)
#define CASE_SIGN_OP(TYPE, name, str) \
CASE_##TYPE##_OP(name##S, str "_s") CASE_##TYPE##_OP(name##U, str "_u")
#define CASE_UNSIGNED_OP(TYPE, name, str) CASE_##TYPE##_OP(name##U, str "_u")
#define CASE_ALL_SIGN_OP(name, str) \
CASE_FLOAT_OP(name, str) CASE_SIGN_OP(INT, name, str)
#define CASE_CONVERT_OP(name, RES, SRC, src_suffix, str) \
CASE_##RES##_OP(U##name##SRC, str "_" src_suffix "_u") \
CASE_##RES##_OP(S##name##SRC, str "_" src_suffix "_s")
#define CASE_CONVERT_SAT_OP(name, RES, SRC, src_suffix, str) \
CASE_##RES##_OP(U##name##Sat##SRC, str "_sat_" src_suffix "_u") \
CASE_##RES##_OP(S##name##Sat##SRC, str "_sat_" src_suffix "_s")
#define CASE_L32_OP(name, str) \
CASE_SIGN_OP(I32, name##8, str "8") \
CASE_SIGN_OP(I32, name##16, str "16") \
@ -185,13 +188,13 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_SIGN_OP(INT, LoadMem8, "load8")
CASE_SIGN_OP(INT, LoadMem16, "load16")
CASE_SIGN_OP(I64, LoadMem32, "load32")
CASE_S128_OP(LoadMem, "load128")
CASE_S128_OP(LoadMem, "load")
CASE_S128_OP(Const, "const")
CASE_ALL_OP(StoreMem, "store")
CASE_INT_OP(StoreMem8, "store8")
CASE_INT_OP(StoreMem16, "store16")
CASE_I64_OP(StoreMem32, "store32")
CASE_S128_OP(StoreMem, "store128")
CASE_S128_OP(StoreMem, "store")
CASE_OP(RefEq, "ref.eq")
CASE_OP(Let, "let")
@ -267,13 +270,13 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_SIMDF_OP(Min, "min")
CASE_SIMDF_OP(Max, "max")
CASE_CONVERT_OP(Convert, F32x4, I32x4, "i32x4", "convert")
CASE_CONVERT_OP(Convert, I32x4, F32x4, "f32x4", "convert")
CASE_CONVERT_OP(Convert, I32x4, I16x8Low, "i16x8_low", "convert")
CASE_CONVERT_OP(Convert, I32x4, I16x8High, "i16x8_high", "convert")
CASE_CONVERT_OP(Convert, I16x8, I32x4, "i32x4", "convert")
CASE_CONVERT_OP(Convert, I16x8, I8x16Low, "i8x16_low", "convert")
CASE_CONVERT_OP(Convert, I16x8, I8x16High, "i8x16_high", "convert")
CASE_CONVERT_OP(Convert, I8x16, I16x8, "i16x8", "convert")
CASE_CONVERT_OP(Convert, I32x4, F32x4, "f32x4", "trunc_sat")
CASE_CONVERT_OP(Convert, I32x4, I16x8Low, "i16x8", "extend_low")
CASE_CONVERT_OP(Convert, I32x4, I16x8High, "i16x8", "extend_high")
CASE_CONVERT_OP(Convert, I16x8, I32x4, "i32x4", "narrow")
CASE_CONVERT_OP(Convert, I16x8, I8x16Low, "i8x16", "extend_low")
CASE_CONVERT_OP(Convert, I16x8, I8x16High, "i8x16", "extend_high")
CASE_CONVERT_OP(Convert, I8x16, I16x8, "i16x8", "narrow")
CASE_SIMDF_OP(ExtractLane, "extract_lane")
CASE_SIMDF_OP(ReplaceLane, "replace_lane")
CASE_I64x2_OP(ExtractLane, "extract_lane")
@ -291,8 +294,8 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_SIGN_OP(SIMDI_NO64X2, Le, "le")
CASE_SIGN_OP(SIMDI_NO64X2, Gt, "gt")
CASE_SIGN_OP(SIMDI_NO64X2, Ge, "ge")
CASE_CONVERT_OP(Convert, I64x2, I32x4Low, "i32x4_low", "convert")
CASE_CONVERT_OP(Convert, I64x2, I32x4High, "i32x4_high", "convert")
CASE_CONVERT_OP(Convert, I64x2, I32x4Low, "i32x4", "extend_low")
CASE_CONVERT_OP(Convert, I64x2, I32x4High, "i32x4", "extend_high")
CASE_SIGN_OP(SIMDI, Shr, "shr")
CASE_SIMDI_OP(Shl, "shl")
CASE_SIGN_OP(I16x8, AddSat, "add_sat")
@ -303,7 +306,7 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_S128_OP(Or, "or")
CASE_S128_OP(Xor, "xor")
CASE_S128_OP(Not, "not")
CASE_S128_OP(Select, "select")
CASE_S128_OP(Select, "bitselect")
CASE_S128_OP(AndNot, "andnot")
CASE_I8x16_OP(Swizzle, "swizzle")
CASE_I8x16_OP(Shuffle, "shuffle")
@ -358,7 +361,7 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_SIGN_OP(I64x2, ExtMulHighI32x4, "extmul_high_i32x4")
CASE_SIGN_OP(I32x4, ExtAddPairwiseI16x8, "extadd_pairwise_i16x8")
CASE_SIGN_OP(I16x8, ExtAddPairwiseI8x16, "extadd_pairwise_i8x6")
CASE_SIGN_OP(I16x8, ExtAddPairwiseI8x16, "extadd_pairwise_i8x16")
CASE_F64x2_OP(ConvertLowI32x4S, "convert_low_i32x4_s")
CASE_F64x2_OP(ConvertLowI32x4U, "convert_low_i32x4_u")
@ -505,9 +508,7 @@ constexpr const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
#undef CASE_I16x8_OP
#undef CASE_I8x16_OP
#undef CASE_S128_OP
#undef CASE_S64x2_OP
#undef CASE_S32x4_OP
#undef CASE_S16x8_OP
#undef CASE_V128_OP
#undef CASE_INT_OP
#undef CASE_FLOAT_OP
#undef CASE_ALL_OP

248
test/unittests/wasm/wasm-opcodes-unittest.cc
View File

@ -14,8 +14,256 @@ class WasmOpcodeTest : public TestWithZone {
void CheckName(WasmOpcode opcode, const char* expected) {
EXPECT_STREQ(expected, WasmOpcodes::OpcodeName(opcode));
}
void CheckSimdName(uint32_t opcode_after_prefix, const char* expected) {
uint32_t raw = kSimdPrefix << (opcode_after_prefix <= 0xFF ? 8 : 12);
raw |= opcode_after_prefix;
WasmOpcode opcode = static_cast<WasmOpcode>(raw);
CheckName(opcode, expected);
}
};
TEST_F(WasmOpcodeTest, SimdNames) {
// Reference:
// https://webassembly.github.io/spec/core/binary/instructions.html#vector-instructions
CheckSimdName(0, "v128.load");
CheckSimdName(1, "v128.load8x8_s");
CheckSimdName(2, "v128.load8x8_u");
CheckSimdName(3, "v128.load16x4_s");
CheckSimdName(4, "v128.load16x4_u");
CheckSimdName(5, "v128.load32x2_s");
CheckSimdName(6, "v128.load32x2_u");
CheckSimdName(7, "v128.load8_splat");
CheckSimdName(8, "v128.load16_splat");
CheckSimdName(9, "v128.load32_splat");
CheckSimdName(10, "v128.load64_splat");
CheckSimdName(92, "v128.load32_zero");
CheckSimdName(93, "v128.load64_zero");
CheckSimdName(11, "v128.store");
CheckSimdName(84, "v128.load8_lane");
CheckSimdName(85, "v128.load16_lane");
CheckSimdName(86, "v128.load32_lane");
CheckSimdName(87, "v128.load64_lane");
CheckSimdName(88, "v128.store8_lane");
CheckSimdName(89, "v128.store16_lane");
CheckSimdName(90, "v128.store32_lane");
CheckSimdName(91, "v128.store64_lane");
CheckSimdName(12, "v128.const");
CheckSimdName(13, "i8x16.shuffle");
CheckSimdName(21, "i8x16.extract_lane_s");
CheckSimdName(22, "i8x16.extract_lane_u");
CheckSimdName(23, "i8x16.replace_lane");
CheckSimdName(24, "i16x8.extract_lane_s");
CheckSimdName(25, "i16x8.extract_lane_u");
CheckSimdName(26, "i16x8.replace_lane");
CheckSimdName(27, "i32x4.extract_lane");
CheckSimdName(28, "i32x4.replace_lane");
CheckSimdName(29, "i64x2.extract_lane");
CheckSimdName(30, "i64x2.replace_lane");
CheckSimdName(31, "f32x4.extract_lane");
CheckSimdName(32, "f32x4.replace_lane");
CheckSimdName(33, "f64x2.extract_lane");
CheckSimdName(34, "f64x2.replace_lane");
CheckSimdName(14, "i8x16.swizzle");
CheckSimdName(15, "i8x16.splat");
CheckSimdName(16, "i16x8.splat");
CheckSimdName(17, "i32x4.splat");
CheckSimdName(18, "i64x2.splat");
CheckSimdName(19, "f32x4.splat");
CheckSimdName(20, "f64x2.splat");
CheckSimdName(35, "i8x16.eq");
CheckSimdName(36, "i8x16.ne");
CheckSimdName(37, "i8x16.lt_s");
CheckSimdName(38, "i8x16.lt_u");
CheckSimdName(39, "i8x16.gt_s");
CheckSimdName(40, "i8x16.gt_u");
CheckSimdName(41, "i8x16.le_s");
CheckSimdName(42, "i8x16.le_u");
CheckSimdName(43, "i8x16.ge_s");
CheckSimdName(44, "i8x16.ge_u");
CheckSimdName(45, "i16x8.eq");
CheckSimdName(46, "i16x8.ne");
CheckSimdName(47, "i16x8.lt_s");
CheckSimdName(48, "i16x8.lt_u");
CheckSimdName(49, "i16x8.gt_s");
CheckSimdName(50, "i16x8.gt_u");
CheckSimdName(51, "i16x8.le_s");
CheckSimdName(52, "i16x8.le_u");
CheckSimdName(53, "i16x8.ge_s");
CheckSimdName(54, "i16x8.ge_u");
CheckSimdName(55, "i32x4.eq");
CheckSimdName(56, "i32x4.ne");
CheckSimdName(57, "i32x4.lt_s");
CheckSimdName(58, "i32x4.lt_u");
CheckSimdName(59, "i32x4.gt_s");
CheckSimdName(60, "i32x4.gt_u");
CheckSimdName(61, "i32x4.le_s");
CheckSimdName(62, "i32x4.le_u");
CheckSimdName(63, "i32x4.ge_s");
CheckSimdName(64, "i32x4.ge_u");
CheckSimdName(214, "i64x2.eq");
CheckSimdName(215, "i64x2.ne");
CheckSimdName(216, "i64x2.lt_s");
CheckSimdName(217, "i64x2.gt_s");
CheckSimdName(218, "i64x2.le_s");
CheckSimdName(219, "i64x2.ge_s");
CheckSimdName(65, "f32x4.eq");
CheckSimdName(66, "f32x4.ne");
CheckSimdName(67, "f32x4.lt");
CheckSimdName(68, "f32x4.gt");
CheckSimdName(69, "f32x4.le");
CheckSimdName(70, "f32x4.ge");
CheckSimdName(71, "f64x2.eq");
CheckSimdName(72, "f64x2.ne");
CheckSimdName(73, "f64x2.lt");
CheckSimdName(74, "f64x2.gt");
CheckSimdName(75, "f64x2.le");
CheckSimdName(76, "f64x2.ge");
CheckSimdName(77, "v128.not");
CheckSimdName(78, "v128.and");
CheckSimdName(79, "v128.andnot");
CheckSimdName(80, "v128.or");
CheckSimdName(81, "v128.xor");
CheckSimdName(82, "v128.bitselect");
CheckSimdName(83, "v128.any_true");
CheckSimdName(96, "i8x16.abs");
CheckSimdName(97, "i8x16.neg");
CheckSimdName(98, "i8x16.popcnt");
CheckSimdName(99, "i8x16.all_true");
CheckSimdName(100, "i8x16.bitmask");
CheckSimdName(101, "i8x16.narrow_i16x8_s");
CheckSimdName(102, "i8x16.narrow_i16x8_u");
CheckSimdName(107, "i8x16.shl");
CheckSimdName(108, "i8x16.shr_s");
CheckSimdName(109, "i8x16.shr_u");
CheckSimdName(110, "i8x16.add");
CheckSimdName(111, "i8x16.add_sat_s");
CheckSimdName(112, "i8x16.add_sat_u");
CheckSimdName(113, "i8x16.sub");
CheckSimdName(114, "i8x16.sub_sat_s");
CheckSimdName(115, "i8x16.sub_sat_u");
CheckSimdName(118, "i8x16.min_s");
CheckSimdName(119, "i8x16.min_u");
CheckSimdName(120, "i8x16.max_s");
CheckSimdName(121, "i8x16.max_u");
CheckSimdName(123, "i8x16.avgr_u");
CheckSimdName(124, "i16x8.extadd_pairwise_i8x16_s");
CheckSimdName(125, "i16x8.extadd_pairwise_i8x16_u");
CheckSimdName(128, "i16x8.abs");
CheckSimdName(129, "i16x8.neg");
CheckSimdName(130, "i16x8.q15mulr_sat_s");
CheckSimdName(131, "i16x8.all_true");
CheckSimdName(132, "i16x8.bitmask");
CheckSimdName(133, "i16x8.narrow_i32x4_s");
CheckSimdName(134, "i16x8.narrow_i32x4_u");
CheckSimdName(135, "i16x8.extend_low_i8x16_s");
CheckSimdName(136, "i16x8.extend_high_i8x16_s");
CheckSimdName(137, "i16x8.extend_low_i8x16_u");
CheckSimdName(138, "i16x8.extend_high_i8x16_u");
CheckSimdName(139, "i16x8.shl");
CheckSimdName(140, "i16x8.shr_s");
CheckSimdName(141, "i16x8.shr_u");
CheckSimdName(142, "i16x8.add");
CheckSimdName(143, "i16x8.add_sat_s");
CheckSimdName(144, "i16x8.add_sat_u");
CheckSimdName(145, "i16x8.sub");
CheckSimdName(146, "i16x8.sub_sat_s");
CheckSimdName(147, "i16x8.sub_sat_u");
CheckSimdName(149, "i16x8.mul");
CheckSimdName(150, "i16x8.min_s");
CheckSimdName(151, "i16x8.min_u");
CheckSimdName(152, "i16x8.max_s");
CheckSimdName(153, "i16x8.max_u");
CheckSimdName(155, "i16x8.avgr_u");
CheckSimdName(156, "i16x8.extmul_low_i8x16_s");
CheckSimdName(157, "i16x8.extmul_high_i8x16_s");
CheckSimdName(158, "i16x8.extmul_low_i8x16_u");
CheckSimdName(159, "i16x8.extmul_high_i8x16_u");
CheckSimdName(126, "i32x4.extadd_pairwise_i16x8_s");
CheckSimdName(127, "i32x4.extadd_pairwise_i16x8_u");
CheckSimdName(160, "i32x4.abs");
CheckSimdName(161, "i32x4.neg");
CheckSimdName(163, "i32x4.all_true");
CheckSimdName(164, "i32x4.bitmask");
CheckSimdName(167, "i32x4.extend_low_i16x8_s");
CheckSimdName(168, "i32x4.extend_high_i16x8_s");
CheckSimdName(169, "i32x4.extend_low_i16x8_u");
CheckSimdName(170, "i32x4.extend_high_i16x8_u");
CheckSimdName(171, "i32x4.shl");
CheckSimdName(172, "i32x4.shr_s");
CheckSimdName(173, "i32x4.shr_u");
CheckSimdName(174, "i32x4.add");
CheckSimdName(177, "i32x4.sub");
CheckSimdName(181, "i32x4.mul");
CheckSimdName(182, "i32x4.min_s");
CheckSimdName(183, "i32x4.min_u");
CheckSimdName(184, "i32x4.max_s");
CheckSimdName(185, "i32x4.max_u");
CheckSimdName(186, "i32x4.dot_i16x8_s");
CheckSimdName(188, "i32x4.extmul_low_i16x8_s");
CheckSimdName(189, "i32x4.extmul_high_i16x8_s");
CheckSimdName(190, "i32x4.extmul_low_i16x8_u");
CheckSimdName(191, "i32x4.extmul_high_i16x8_u");
CheckSimdName(192, "i64x2.abs");
CheckSimdName(193, "i64x2.neg");
CheckSimdName(195, "i64x2.all_true");
CheckSimdName(196, "i64x2.bitmask");
CheckSimdName(199, "i64x2.extend_low_i32x4_s");
CheckSimdName(200, "i64x2.extend_high_i32x4_s");
CheckSimdName(201, "i64x2.extend_low_i32x4_u");
CheckSimdName(202, "i64x2.extend_high_i32x4_u");
CheckSimdName(203, "i64x2.shl");
CheckSimdName(204, "i64x2.shr_s");
CheckSimdName(205, "i64x2.shr_u");
CheckSimdName(206, "i64x2.add");
CheckSimdName(209, "i64x2.sub");
CheckSimdName(213, "i64x2.mul");
CheckSimdName(220, "i64x2.extmul_low_i32x4_s");
CheckSimdName(221, "i64x2.extmul_high_i32x4_s");
CheckSimdName(222, "i64x2.extmul_low_i32x4_u");
CheckSimdName(223, "i64x2.extmul_high_i32x4_u");
CheckSimdName(103, "f32x4.ceil");
CheckSimdName(104, "f32x4.floor");
CheckSimdName(105, "f32x4.trunc");
CheckSimdName(106, "f32x4.nearest");
CheckSimdName(224, "f32x4.abs");
CheckSimdName(225, "f32x4.neg");
CheckSimdName(227, "f32x4.sqrt");
CheckSimdName(228, "f32x4.add");
CheckSimdName(229, "f32x4.sub");
CheckSimdName(230, "f32x4.mul");
CheckSimdName(231, "f32x4.div");
CheckSimdName(232, "f32x4.min");
CheckSimdName(233, "f32x4.max");
CheckSimdName(234, "f32x4.pmin");
CheckSimdName(235, "f32x4.pmax");
CheckSimdName(116, "f64x2.ceil");
CheckSimdName(117, "f64x2.floor");
CheckSimdName(122, "f64x2.trunc");
CheckSimdName(148, "f64x2.nearest");
CheckSimdName(236, "f64x2.abs");
CheckSimdName(237, "f64x2.neg");
CheckSimdName(239, "f64x2.sqrt");
CheckSimdName(240, "f64x2.add");
CheckSimdName(241, "f64x2.sub");
CheckSimdName(242, "f64x2.mul");
CheckSimdName(243, "f64x2.div");
CheckSimdName(244, "f64x2.min");
CheckSimdName(245, "f64x2.max");
CheckSimdName(246, "f64x2.pmin");
CheckSimdName(247, "f64x2.pmax");
CheckSimdName(248, "i32x4.trunc_sat_f32x4_s");
CheckSimdName(249, "i32x4.trunc_sat_f32x4_u");
CheckSimdName(250, "f32x4.convert_i32x4_s");
CheckSimdName(251, "f32x4.convert_i32x4_u");
CheckSimdName(252, "i32x4.trunc_sat_f64x2_s_zero");
CheckSimdName(253, "i32x4.trunc_sat_f64x2_u_zero");
CheckSimdName(254, "f64x2.convert_low_i32x4_s");
CheckSimdName(255, "f64x2.convert_low_i32x4_u");
CheckSimdName(94, "f32x4.demote_f64x2_zero");
CheckSimdName(95, "f64x2.promote_low_f32x4");
}
TEST_F(WasmOpcodeTest, AtomicNames) {
// Reference:
// https://webassembly.github.io/threads/core/text/instructions.html#atomic-memory-instructions