[ARM] Macro-ize SIMD visitors in InstructionSelector.
- Uses macros for splat, extract lane, replace lane, unary ops and binary ops. - Renames ARM SIMD instruction codes to match machine operator names. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2652893013 Cr-Commit-Position: refs/heads/master@{#42799}
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@ -1545,12 +1545,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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i.InputSimd128Register(1));
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break;
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}
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case kArmFloat32x4Eq: {
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case kArmFloat32x4Equal: {
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__ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmFloat32x4Ne: {
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case kArmFloat32x4NotEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1));
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__ vmvn(dst, dst);
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@ -1607,35 +1607,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt32x4Eq: {
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case kArmInt32x4Equal: {
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__ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt32x4Ne: {
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case kArmInt32x4NotEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vceq(Neon32, dst, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vmvn(dst, dst);
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break;
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}
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case kArmInt32x4Gt: {
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case kArmInt32x4GreaterThan: {
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__ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt32x4Ge: {
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case kArmInt32x4GreaterThanOrEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vcge(NeonS32, dst, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmUint32x4Gt: {
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case kArmUint32x4GreaterThan: {
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__ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmUint32x4Ge: {
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case kArmUint32x4GreaterThanOrEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vcge(NeonU32, dst, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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@ -1693,35 +1693,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt16x8Eq: {
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case kArmInt16x8Equal: {
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__ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt16x8Ne: {
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case kArmInt16x8NotEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vceq(Neon16, dst, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vmvn(dst, dst);
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break;
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}
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case kArmInt16x8Gt: {
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case kArmInt16x8GreaterThan: {
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__ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt16x8Ge: {
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case kArmInt16x8GreaterThanOrEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vcge(NeonS16, dst, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmUint16x8Gt: {
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case kArmUint16x8GreaterThan: {
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__ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmUint16x8Ge: {
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case kArmUint16x8GreaterThanOrEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vcge(NeonU16, dst, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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@ -1770,34 +1770,34 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt8x16Eq: {
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case kArmInt8x16Equal: {
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__ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt8x16Ne: {
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case kArmInt8x16NotEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1));
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__ vmvn(dst, dst);
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break;
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}
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case kArmInt8x16Gt: {
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case kArmInt8x16GreaterThan: {
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__ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmInt8x16Ge: {
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case kArmInt8x16GreaterThanOrEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vcge(NeonS8, dst, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmUint8x16Gt: {
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case kArmUint8x16GreaterThan: {
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__ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kArmUint8x16Ge: {
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case kArmUint8x16GreaterThanOrEqual: {
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Simd128Register dst = i.OutputSimd128Register();
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__ vcge(NeonU8, dst, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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@ -129,8 +129,8 @@ namespace compiler {
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V(ArmFloat32x4Neg) \
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V(ArmFloat32x4Add) \
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V(ArmFloat32x4Sub) \
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V(ArmFloat32x4Eq) \
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V(ArmFloat32x4Ne) \
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V(ArmFloat32x4Equal) \
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V(ArmFloat32x4NotEqual) \
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V(ArmInt32x4Splat) \
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V(ArmInt32x4ExtractLane) \
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V(ArmInt32x4ReplaceLane) \
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@ -142,12 +142,12 @@ namespace compiler {
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V(ArmInt32x4Mul) \
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V(ArmInt32x4Min) \
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V(ArmInt32x4Max) \
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V(ArmInt32x4Eq) \
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V(ArmInt32x4Ne) \
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V(ArmInt32x4Gt) \
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V(ArmInt32x4Ge) \
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V(ArmUint32x4Gt) \
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V(ArmUint32x4Ge) \
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V(ArmInt32x4Equal) \
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V(ArmInt32x4NotEqual) \
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V(ArmInt32x4GreaterThan) \
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V(ArmInt32x4GreaterThanOrEqual) \
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V(ArmUint32x4GreaterThan) \
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V(ArmUint32x4GreaterThanOrEqual) \
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V(ArmSimd32x4Select) \
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V(ArmInt16x8Splat) \
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V(ArmInt16x8ExtractLane) \
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@ -158,12 +158,12 @@ namespace compiler {
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V(ArmInt16x8Mul) \
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V(ArmInt16x8Min) \
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V(ArmInt16x8Max) \
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V(ArmInt16x8Eq) \
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V(ArmInt16x8Ne) \
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V(ArmInt16x8Gt) \
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V(ArmInt16x8Ge) \
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V(ArmUint16x8Gt) \
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V(ArmUint16x8Ge) \
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V(ArmInt16x8Equal) \
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V(ArmInt16x8NotEqual) \
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V(ArmInt16x8GreaterThan) \
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V(ArmInt16x8GreaterThanOrEqual) \
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V(ArmUint16x8GreaterThan) \
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V(ArmUint16x8GreaterThanOrEqual) \
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V(ArmInt8x16Splat) \
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V(ArmInt8x16ExtractLane) \
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V(ArmInt8x16ReplaceLane) \
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@ -173,12 +173,12 @@ namespace compiler {
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V(ArmInt8x16Mul) \
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V(ArmInt8x16Min) \
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V(ArmInt8x16Max) \
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V(ArmInt8x16Eq) \
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V(ArmInt8x16Ne) \
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V(ArmInt8x16Gt) \
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V(ArmInt8x16Ge) \
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V(ArmUint8x16Gt) \
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V(ArmUint8x16Ge)
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V(ArmInt8x16Equal) \
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V(ArmInt8x16NotEqual) \
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V(ArmInt8x16GreaterThan) \
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V(ArmInt8x16GreaterThanOrEqual) \
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V(ArmUint8x16GreaterThan) \
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V(ArmUint8x16GreaterThanOrEqual)
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// Addressing modes represent the "shape" of inputs to an instruction.
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// Many instructions support multiple addressing modes. Addressing modes
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@ -117,8 +117,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kArmFloat32x4Neg:
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case kArmFloat32x4Add:
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case kArmFloat32x4Sub:
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case kArmFloat32x4Eq:
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case kArmFloat32x4Ne:
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case kArmFloat32x4Equal:
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case kArmFloat32x4NotEqual:
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case kArmInt32x4Splat:
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case kArmInt32x4ExtractLane:
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case kArmInt32x4ReplaceLane:
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@ -130,12 +130,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kArmInt32x4Mul:
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case kArmInt32x4Min:
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case kArmInt32x4Max:
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case kArmInt32x4Eq:
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case kArmInt32x4Ne:
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case kArmInt32x4Gt:
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case kArmInt32x4Ge:
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case kArmUint32x4Gt:
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case kArmUint32x4Ge:
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case kArmInt32x4Equal:
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case kArmInt32x4NotEqual:
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case kArmInt32x4GreaterThan:
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case kArmInt32x4GreaterThanOrEqual:
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case kArmUint32x4GreaterThan:
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case kArmUint32x4GreaterThanOrEqual:
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case kArmSimd32x4Select:
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case kArmInt16x8Splat:
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case kArmInt16x8ExtractLane:
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@ -146,12 +146,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kArmInt16x8Mul:
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case kArmInt16x8Min:
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case kArmInt16x8Max:
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case kArmInt16x8Eq:
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case kArmInt16x8Ne:
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case kArmInt16x8Gt:
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case kArmInt16x8Ge:
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case kArmUint16x8Gt:
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case kArmUint16x8Ge:
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case kArmInt16x8Equal:
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case kArmInt16x8NotEqual:
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case kArmInt16x8GreaterThan:
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case kArmInt16x8GreaterThanOrEqual:
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case kArmUint16x8GreaterThan:
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case kArmUint16x8GreaterThanOrEqual:
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case kArmInt8x16Splat:
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case kArmInt8x16ExtractLane:
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case kArmInt8x16ReplaceLane:
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@ -161,12 +161,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kArmInt8x16Mul:
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case kArmInt8x16Min:
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case kArmInt8x16Max:
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case kArmInt8x16Eq:
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case kArmInt8x16Ne:
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case kArmInt8x16Gt:
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case kArmInt8x16Ge:
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case kArmUint8x16Gt:
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case kArmUint8x16Ge:
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case kArmInt8x16Equal:
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case kArmInt8x16NotEqual:
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case kArmInt8x16GreaterThan:
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case kArmInt8x16GreaterThanOrEqual:
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case kArmUint8x16GreaterThan:
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case kArmUint8x16GreaterThanOrEqual:
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return kNoOpcodeFlags;
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case kArmVldrF32:
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@ -92,6 +92,20 @@ void VisitRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
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g.UseRegister(node->InputAt(1)));
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}
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void VisitRRI(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
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ArmOperandGenerator g(selector);
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int32_t imm = OpParameter<int32_t>(node);
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selector->Emit(opcode, g.DefineAsRegister(node),
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g.UseRegister(node->InputAt(0)), g.UseImmediate(imm));
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}
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void VisitRRIR(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
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ArmOperandGenerator g(selector);
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int32_t imm = OpParameter<int32_t>(node);
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selector->Emit(opcode, g.DefineAsRegister(node),
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g.UseRegister(node->InputAt(0)), g.UseImmediate(imm),
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g.UseRegister(node->InputAt(1)));
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}
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template <IrOpcode::Value kOpcode, int kImmMin, int kImmMax,
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AddressingMode kImmMode, AddressingMode kRegMode>
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@ -1090,15 +1104,8 @@ void InstructionSelector::VisitWord32Ror(Node* node) {
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VisitShift(this, node, TryMatchROR);
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}
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void InstructionSelector::VisitWord32Clz(Node* node) {
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VisitRR(this, kArmClz, node);
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}
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void InstructionSelector::VisitWord32Ctz(Node* node) { UNREACHABLE(); }
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void InstructionSelector::VisitWord32ReverseBits(Node* node) {
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DCHECK(IsSupported(ARMv7));
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VisitRR(this, kArmRbit, node);
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@ -1299,12 +1306,6 @@ void InstructionSelector::VisitInt32Mul(Node* node) {
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VisitRRR(this, kArmMul, node);
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}
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void InstructionSelector::VisitInt32MulHigh(Node* node) {
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VisitRRR(this, kArmSmmul, node);
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}
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void InstructionSelector::VisitUint32MulHigh(Node* node) {
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ArmOperandGenerator g(this);
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InstructionOperand outputs[] = {g.TempRegister(), g.DefineAsRegister(node)};
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@ -1333,73 +1334,76 @@ void InstructionSelector::VisitUint32Mod(Node* node) {
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VisitMod(this, node, kArmUdiv, kArmVcvtF64U32, kArmVcvtU32F64);
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}
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#define RR_OP_LIST(V) \
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V(Word32Clz, kArmClz) \
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V(ChangeFloat32ToFloat64, kArmVcvtF64F32) \
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V(RoundInt32ToFloat32, kArmVcvtF32S32) \
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V(RoundUint32ToFloat32, kArmVcvtF32U32) \
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V(ChangeInt32ToFloat64, kArmVcvtF64S32) \
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V(ChangeUint32ToFloat64, kArmVcvtF64U32) \
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V(TruncateFloat32ToInt32, kArmVcvtS32F32) \
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V(TruncateFloat32ToUint32, kArmVcvtU32F32) \
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V(ChangeFloat64ToInt32, kArmVcvtS32F64) \
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V(ChangeFloat64ToUint32, kArmVcvtU32F64) \
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V(TruncateFloat64ToUint32, kArmVcvtU32F64) \
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V(TruncateFloat64ToFloat32, kArmVcvtF32F64) \
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V(TruncateFloat64ToWord32, kArchTruncateDoubleToI) \
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V(RoundFloat64ToInt32, kArmVcvtS32F64) \
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V(BitcastFloat32ToInt32, kArmVmovU32F32) \
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V(BitcastInt32ToFloat32, kArmVmovF32U32) \
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V(Float64ExtractLowWord32, kArmVmovLowU32F64) \
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V(Float64ExtractHighWord32, kArmVmovHighU32F64) \
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V(Float64SilenceNaN, kArmFloat64SilenceNaN) \
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V(Float32Abs, kArmVabsF32) \
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V(Float64Abs, kArmVabsF64) \
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V(Float32Neg, kArmVnegF32) \
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V(Float64Neg, kArmVnegF64) \
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V(Float32Sqrt, kArmVsqrtF32) \
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V(Float64Sqrt, kArmVsqrtF64)
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void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
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VisitRR(this, kArmVcvtF64F32, node);
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}
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#define RR_OP_LIST_V8(V) \
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V(Float32RoundDown, kArmVrintmF32) \
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V(Float64RoundDown, kArmVrintmF64) \
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V(Float32RoundUp, kArmVrintpF32) \
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V(Float64RoundUp, kArmVrintpF64) \
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V(Float32RoundTruncate, kArmVrintzF32) \
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V(Float64RoundTruncate, kArmVrintzF64) \
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V(Float64RoundTiesAway, kArmVrintaF64) \
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V(Float32RoundTiesEven, kArmVrintnF32) \
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V(Float64RoundTiesEven, kArmVrintnF64)
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#define RRR_OP_LIST(V) \
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V(Int32MulHigh, kArmSmmul) \
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V(Float32Mul, kArmVmulF32) \
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V(Float64Mul, kArmVmulF64) \
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V(Float32Div, kArmVdivF32) \
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V(Float64Div, kArmVdivF64) \
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V(Float32Max, kArmFloat32Max) \
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V(Float64Max, kArmFloat64Max) \
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V(Float32Min, kArmFloat32Min) \
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V(Float64Min, kArmFloat64Min)
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void InstructionSelector::VisitRoundInt32ToFloat32(Node* node) {
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VisitRR(this, kArmVcvtF32S32, node);
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}
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#define RR_VISITOR(Name, opcode) \
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void InstructionSelector::Visit##Name(Node* node) { \
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VisitRR(this, opcode, node); \
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}
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RR_OP_LIST(RR_VISITOR)
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#undef RR_VISITOR
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#define RR_VISITOR_V8(Name, opcode) \
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void InstructionSelector::Visit##Name(Node* node) { \
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DCHECK(CpuFeatures::IsSupported(ARMv8)); \
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VisitRR(this, opcode, node); \
|
||||
}
|
||||
RR_OP_LIST_V8(RR_VISITOR_V8)
|
||||
#undef RR_VISITOR_V8
|
||||
|
||||
void InstructionSelector::VisitRoundUint32ToFloat32(Node* node) {
|
||||
VisitRR(this, kArmVcvtF32U32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) {
|
||||
VisitRR(this, kArmVcvtF64S32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) {
|
||||
VisitRR(this, kArmVcvtF64U32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitTruncateFloat32ToInt32(Node* node) {
|
||||
VisitRR(this, kArmVcvtS32F32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitTruncateFloat32ToUint32(Node* node) {
|
||||
VisitRR(this, kArmVcvtU32F32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitChangeFloat64ToInt32(Node* node) {
|
||||
VisitRR(this, kArmVcvtS32F64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
|
||||
VisitRR(this, kArmVcvtU32F64, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitTruncateFloat64ToUint32(Node* node) {
|
||||
VisitRR(this, kArmVcvtU32F64, node);
|
||||
}
|
||||
void InstructionSelector::VisitTruncateFloat64ToFloat32(Node* node) {
|
||||
VisitRR(this, kArmVcvtF32F64, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitTruncateFloat64ToWord32(Node* node) {
|
||||
VisitRR(this, kArchTruncateDoubleToI, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitRoundFloat64ToInt32(Node* node) {
|
||||
VisitRR(this, kArmVcvtS32F64, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) {
|
||||
VisitRR(this, kArmVmovU32F32, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitBitcastInt32ToFloat32(Node* node) {
|
||||
VisitRR(this, kArmVmovF32U32, node);
|
||||
}
|
||||
#define RRR_VISITOR(Name, opcode) \
|
||||
void InstructionSelector::Visit##Name(Node* node) { \
|
||||
VisitRRR(this, opcode, node); \
|
||||
}
|
||||
RRR_OP_LIST(RRR_VISITOR)
|
||||
#undef RRR_VISITOR
|
||||
|
||||
void InstructionSelector::VisitFloat32Add(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
@ -1468,132 +1472,12 @@ void InstructionSelector::VisitFloat64Sub(Node* node) {
|
||||
VisitRRR(this, kArmVsubF64, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32Mul(Node* node) {
|
||||
VisitRRR(this, kArmVmulF32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64Mul(Node* node) {
|
||||
VisitRRR(this, kArmVmulF64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat32Div(Node* node) {
|
||||
VisitRRR(this, kArmVdivF32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64Div(Node* node) {
|
||||
VisitRRR(this, kArmVdivF64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64Mod(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmVmodF64, g.DefineAsFixed(node, d0), g.UseFixed(node->InputAt(0), d0),
|
||||
g.UseFixed(node->InputAt(1), d1))->MarkAsCall();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32Max(Node* node) {
|
||||
VisitRRR(this, kArmFloat32Max, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat64Max(Node* node) {
|
||||
VisitRRR(this, kArmFloat64Max, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat64SilenceNaN(Node* node) {
|
||||
VisitRR(this, kArmFloat64SilenceNaN, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32Min(Node* node) {
|
||||
VisitRRR(this, kArmFloat32Min, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat64Min(Node* node) {
|
||||
VisitRRR(this, kArmFloat64Min, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32Abs(Node* node) {
|
||||
VisitRR(this, kArmVabsF32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64Abs(Node* node) {
|
||||
VisitRR(this, kArmVabsF64, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32Sqrt(Node* node) {
|
||||
VisitRR(this, kArmVsqrtF32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64Sqrt(Node* node) {
|
||||
VisitRR(this, kArmVsqrtF64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat32RoundDown(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintmF32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64RoundDown(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintmF64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat32RoundUp(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintpF32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64RoundUp(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintpF64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat32RoundTruncate(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintzF32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64RoundTruncate(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintzF64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintaF64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintnF32, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
|
||||
DCHECK(CpuFeatures::IsSupported(ARMv8));
|
||||
VisitRR(this, kArmVrintnF64, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32Neg(Node* node) {
|
||||
VisitRR(this, kArmVnegF32, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat64Neg(Node* node) {
|
||||
VisitRR(this, kArmVnegF64, node);
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat64Ieee754Binop(Node* node,
|
||||
InstructionCode opcode) {
|
||||
ArmOperandGenerator g(this);
|
||||
@ -2188,17 +2072,6 @@ void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) {
|
||||
VisitFloat64Compare(this, node, &cont);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64ExtractLowWord32(Node* node) {
|
||||
VisitRR(this, kArmVmovLowU32F64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) {
|
||||
VisitRR(this, kArmVmovHighU32F64, node);
|
||||
}
|
||||
|
||||
|
||||
void InstructionSelector::VisitFloat64InsertLowWord32(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Node* left = node->InputAt(0);
|
||||
@ -2286,178 +2159,96 @@ void InstructionSelector::VisitAtomicStore(Node* node) {
|
||||
Emit(code, 0, nullptr, input_count, inputs);
|
||||
}
|
||||
|
||||
// TODO(bbudge) Macro-ize SIMD methods.
|
||||
void InstructionSelector::VisitCreateFloat32x4(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
|
||||
}
|
||||
#define SIMD_TYPE_LIST(V) \
|
||||
V(Float32x4) \
|
||||
V(Int32x4) \
|
||||
V(Int16x8) \
|
||||
V(Int8x16)
|
||||
|
||||
void InstructionSelector::VisitFloat32x4ExtractLane(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
int32_t lane = OpParameter<int32_t>(node);
|
||||
Emit(kArmFloat32x4ExtractLane, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
|
||||
}
|
||||
#define SIMD_UNOP_LIST(V) \
|
||||
V(Float32x4FromInt32x4) \
|
||||
V(Float32x4FromUint32x4) \
|
||||
V(Float32x4Abs) \
|
||||
V(Float32x4Neg) \
|
||||
V(Int32x4FromFloat32x4) \
|
||||
V(Uint32x4FromFloat32x4) \
|
||||
V(Int32x4Neg) \
|
||||
V(Int16x8Neg) \
|
||||
V(Int8x16Neg)
|
||||
|
||||
void InstructionSelector::VisitFloat32x4ReplaceLane(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
int32_t lane = OpParameter<int32_t>(node);
|
||||
Emit(kArmFloat32x4ReplaceLane, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
|
||||
g.Use(node->InputAt(1)));
|
||||
}
|
||||
#define SIMD_BINOP_LIST(V) \
|
||||
V(Float32x4Add) \
|
||||
V(Float32x4Sub) \
|
||||
V(Float32x4Equal) \
|
||||
V(Float32x4NotEqual) \
|
||||
V(Int32x4Add) \
|
||||
V(Int32x4Sub) \
|
||||
V(Int32x4Mul) \
|
||||
V(Int32x4Min) \
|
||||
V(Int32x4Max) \
|
||||
V(Int32x4Equal) \
|
||||
V(Int32x4NotEqual) \
|
||||
V(Int32x4GreaterThan) \
|
||||
V(Int32x4GreaterThanOrEqual) \
|
||||
V(Uint32x4GreaterThan) \
|
||||
V(Uint32x4GreaterThanOrEqual) \
|
||||
V(Int16x8Add) \
|
||||
V(Int16x8Sub) \
|
||||
V(Int16x8Mul) \
|
||||
V(Int16x8Min) \
|
||||
V(Int16x8Max) \
|
||||
V(Int16x8Equal) \
|
||||
V(Int16x8NotEqual) \
|
||||
V(Int16x8GreaterThan) \
|
||||
V(Int16x8GreaterThanOrEqual) \
|
||||
V(Uint16x8GreaterThan) \
|
||||
V(Uint16x8GreaterThanOrEqual) \
|
||||
V(Int8x16Add) \
|
||||
V(Int8x16Sub) \
|
||||
V(Int8x16Mul) \
|
||||
V(Int8x16Min) \
|
||||
V(Int8x16Max) \
|
||||
V(Int8x16Equal) \
|
||||
V(Int8x16NotEqual) \
|
||||
V(Int8x16GreaterThan) \
|
||||
V(Int8x16GreaterThanOrEqual) \
|
||||
V(Uint8x16GreaterThan) \
|
||||
V(Uint8x16GreaterThanOrEqual)
|
||||
|
||||
void InstructionSelector::VisitFloat32x4FromInt32x4(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4FromInt32x4, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
#define SIMD_VISIT_SPLAT(Type) \
|
||||
void InstructionSelector::VisitCreate##Type(Node* node) { \
|
||||
VisitRR(this, kArm##Type##Splat, node); \
|
||||
}
|
||||
SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
|
||||
#undef SIMD_VISIT_SPLAT
|
||||
|
||||
void InstructionSelector::VisitFloat32x4FromUint32x4(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4FromUint32x4, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
#define SIMD_VISIT_EXTRACT_LANE(Type) \
|
||||
void InstructionSelector::Visit##Type##ExtractLane(Node* node) { \
|
||||
VisitRRI(this, kArm##Type##ExtractLane, node); \
|
||||
}
|
||||
SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
|
||||
#undef SIMD_VISIT_EXTRACT_LANE
|
||||
|
||||
void InstructionSelector::VisitFloat32x4Abs(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4Abs, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
#define SIMD_VISIT_REPLACE_LANE(Type) \
|
||||
void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
|
||||
VisitRRIR(this, kArm##Type##ReplaceLane, node); \
|
||||
}
|
||||
SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
|
||||
#undef SIMD_VISIT_REPLACE_LANE
|
||||
|
||||
void InstructionSelector::VisitFloat32x4Neg(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4Neg, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
#define SIMD_VISIT_UNOP(Name) \
|
||||
void InstructionSelector::Visit##Name(Node* node) { \
|
||||
VisitRR(this, kArm##Name, node); \
|
||||
}
|
||||
SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
|
||||
#undef SIMD_VISIT_UNOP
|
||||
|
||||
void InstructionSelector::VisitFloat32x4Add(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4Add, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32x4Sub(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4Sub, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32x4Equal(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4Eq, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitFloat32x4NotEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmFloat32x4Ne, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitCreateInt32x4(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4ExtractLane(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
int32_t lane = OpParameter<int32_t>(node);
|
||||
Emit(kArmInt32x4ExtractLane, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4ReplaceLane(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
int32_t lane = OpParameter<int32_t>(node);
|
||||
Emit(kArmInt32x4ReplaceLane, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
|
||||
g.Use(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4FromFloat32x4(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4FromFloat32x4, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitUint32x4FromFloat32x4(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmUint32x4FromFloat32x4, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4Neg(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Neg, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4Add(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Add, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4Sub(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Sub, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4Mul(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Mul, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4Min(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Min, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4Max(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Max, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4Equal(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4NotEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4GreaterThan(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt32x4GreaterThanOrEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt32x4Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitUint32x4GreaterThan(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmUint32x4Gt, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitUint32x4GreaterThanOrEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmUint32x4Ge, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
#define SIMD_VISIT_BINOP(Name) \
|
||||
void InstructionSelector::Visit##Name(Node* node) { \
|
||||
VisitRRR(this, kArm##Name, node); \
|
||||
}
|
||||
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
|
||||
#undef SIMD_VISIT_BINOP
|
||||
|
||||
void InstructionSelector::VisitSimd32x4Select(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
@ -2466,190 +2257,6 @@ void InstructionSelector::VisitSimd32x4Select(Node* node) {
|
||||
g.UseRegister(node->InputAt(2)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitCreateInt16x8(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8ExtractLane(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
int32_t lane = OpParameter<int32_t>(node);
|
||||
Emit(kArmInt16x8ExtractLane, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8ReplaceLane(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
int32_t lane = OpParameter<int32_t>(node);
|
||||
Emit(kArmInt16x8ReplaceLane, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
|
||||
g.Use(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8Neg(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Neg, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8Add(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Add, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8Sub(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Sub, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8Mul(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Mul, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8Min(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Min, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8Max(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Max, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8Equal(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8NotEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8GreaterThan(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt16x8GreaterThanOrEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt16x8Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitUint16x8GreaterThan(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmUint16x8Gt, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitUint16x8GreaterThanOrEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmUint16x8Ge, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitCreateInt8x16(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16ExtractLane(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
int32_t lane = OpParameter<int32_t>(node);
|
||||
Emit(kArmInt8x16ExtractLane, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16ReplaceLane(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
int32_t lane = OpParameter<int32_t>(node);
|
||||
Emit(kArmInt8x16ReplaceLane, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
|
||||
g.Use(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16Neg(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Neg, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16Add(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Add, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16Sub(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Sub, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16Mul(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Mul, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16Min(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Min, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16Max(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Max, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16Equal(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Eq, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16NotEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Ne, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16GreaterThan(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Gt, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitInt8x16GreaterThanOrEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmInt8x16Ge, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)),
|
||||
g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitUint8x16GreaterThan(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmUint8x16Gt, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitUint8x16GreaterThanOrEqual(Node* node) {
|
||||
ArmOperandGenerator g(this);
|
||||
Emit(kArmUint8x16Ge, g.DefineAsRegister(node),
|
||||
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
|
||||
}
|
||||
|
||||
// static
|
||||
MachineOperatorBuilder::Flags
|
||||
InstructionSelector::SupportedMachineOperatorFlags() {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user