PPC/s390: [assembler] Unify RelocInfo::NONE32 and NONE64
Port d3a4d15f5e
Original Commit Message:
This reloc mode is never encoded, so there is no reason to
differentiate between 32 and 64 bit.
Both are now replaced by RelocInfo::NONE.
R=clemensh@chromium.org, joransiu@ca.ibm.com, bjaideep@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=
LOG=N
Change-Id: I9a5369315cc2c966bffd3862d15f29aea08960e4
Reviewed-on: https://chromium-review.googlesource.com/881463
Reviewed-by: Joran Siu <joransiu@ca.ibm.com>
Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#50815}
This commit is contained in:
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a9796a1d27
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@ -241,7 +241,7 @@ void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) {
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}
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}
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Operand::Operand(Register rm) : rm_(rm), rmode_(kRelocInfo_NONEPTR) {}
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Operand::Operand(Register rm) : rm_(rm), rmode_(RelocInfo::NONE) {}
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void Assembler::UntrackBranch() {
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DCHECK(!trampoline_emitted_);
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@ -221,7 +221,7 @@ void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) {
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}
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// Operand constructors
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Operand::Operand(Register rm) : rm_(rm), rmode_(kRelocInfo_NONEPTR) {}
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Operand::Operand(Register rm) : rm_(rm), rmode_(RelocInfo::NONE) {}
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int32_t Assembler::emit_code_target(Handle<Code> target,
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RelocInfo::Mode rmode) {
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@ -1049,7 +1049,7 @@ void MacroAssembler::LeaveExitFrame(bool save_doubles, Register argument_count,
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// Clear top frame.
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mov(ip, Operand(ExternalReference(IsolateAddressId::kCEntryFPAddress,
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isolate())));
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StoreP(MemOperand(ip), Operand(0, kRelocInfo_NONEPTR), r0);
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StoreP(MemOperand(ip), Operand(0, RelocInfo::NONE), r0);
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// Restore current context from top and clear it in debug mode.
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mov(ip,
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@ -1947,7 +1947,7 @@ void TurboAssembler::mov(Register dst, const Operand& src) {
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value = src.immediate();
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}
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if (src.rmode() != kRelocInfo_NONEPTR) {
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if (src.rmode() != RelocInfo::NONE) {
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// some form of relocation needed
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RecordRelocInfo(src.rmode(), value);
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}
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@ -3166,7 +3166,7 @@ void TurboAssembler::CmpP(Register src1, Register src2) {
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// Compare 32-bit Register vs Immediate
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// This helper will set up proper relocation entries if required.
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void TurboAssembler::Cmp32(Register dst, const Operand& opnd) {
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if (opnd.rmode() == kRelocInfo_NONEPTR) {
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if (opnd.rmode() == RelocInfo::NONE) {
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intptr_t value = opnd.immediate();
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if (is_int16(value))
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chi(dst, opnd);
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@ -3183,7 +3183,7 @@ void TurboAssembler::Cmp32(Register dst, const Operand& opnd) {
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// This helper will set up proper relocation entries if required.
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void TurboAssembler::CmpP(Register dst, const Operand& opnd) {
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#if V8_TARGET_ARCH_S390X
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if (opnd.rmode() == kRelocInfo_NONEPTR) {
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if (opnd.rmode() == RelocInfo::NONE) {
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cgfi(dst, opnd);
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} else {
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mov(r0, opnd); // Need to generate 64-bit relocation
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@ -3470,7 +3470,7 @@ void TurboAssembler::StoreP(Register src, const MemOperand& mem,
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void TurboAssembler::StoreP(const MemOperand& mem, const Operand& opnd,
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Register scratch) {
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// Relocations not supported
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DCHECK_EQ(opnd.rmode(), kRelocInfo_NONEPTR);
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DCHECK_EQ(opnd.rmode(), RelocInfo::NONE);
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// Try to use MVGHI/MVHI
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if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT) && is_uint12(mem.offset()) &&
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@ -87,7 +87,7 @@ TEST(1) {
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#endif
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__ lr(r3, r2);
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__ lhi(r2, Operand(0, kRelocInfo_NONEPTR));
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__ lhi(r2, Operand(0, RelocInfo::NONE));
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__ b(&C);
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__ bind(&L);
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@ -95,7 +95,7 @@ TEST(1) {
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__ ahi(r3, Operand(-1 & 0xFFFF));
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__ bind(&C);
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__ cfi(r3, Operand(0, kRelocInfo_NONEPTR));
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__ cfi(r3, Operand(0, RelocInfo::NONE));
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__ bne(&L);
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__ b(r14);
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@ -137,7 +137,7 @@ TEST(2) {
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__ ahi(r3, Operand(-1 & 0xFFFF));
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__ bind(&C);
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__ cfi(r3, Operand(0, kRelocInfo_NONEPTR));
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__ cfi(r3, Operand(0, RelocInfo::NONE));
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__ bne(&L);
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__ b(r14);
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