PPC/s390: [assembler] Unify RelocInfo::NONE32 and NONE64

Port d3a4d15f5e

Original Commit Message:

    This reloc mode is never encoded, so there is no reason to
    differentiate between 32 and 64 bit.
    Both are now replaced by RelocInfo::NONE.

R=clemensh@chromium.org, joransiu@ca.ibm.com, bjaideep@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=
LOG=N

Change-Id: I9a5369315cc2c966bffd3862d15f29aea08960e4
Reviewed-on: https://chromium-review.googlesource.com/881463
Reviewed-by: Joran Siu <joransiu@ca.ibm.com>
Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#50815}
This commit is contained in:
Junliang Yan 2018-01-23 13:34:40 -05:00 committed by Commit Bot
parent a9796a1d27
commit c13fd598d7
4 changed files with 10 additions and 10 deletions

View File

@ -241,7 +241,7 @@ void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) {
}
}
Operand::Operand(Register rm) : rm_(rm), rmode_(kRelocInfo_NONEPTR) {}
Operand::Operand(Register rm) : rm_(rm), rmode_(RelocInfo::NONE) {}
void Assembler::UntrackBranch() {
DCHECK(!trampoline_emitted_);

View File

@ -221,7 +221,7 @@ void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) {
}
// Operand constructors
Operand::Operand(Register rm) : rm_(rm), rmode_(kRelocInfo_NONEPTR) {}
Operand::Operand(Register rm) : rm_(rm), rmode_(RelocInfo::NONE) {}
int32_t Assembler::emit_code_target(Handle<Code> target,
RelocInfo::Mode rmode) {

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@ -1049,7 +1049,7 @@ void MacroAssembler::LeaveExitFrame(bool save_doubles, Register argument_count,
// Clear top frame.
mov(ip, Operand(ExternalReference(IsolateAddressId::kCEntryFPAddress,
isolate())));
StoreP(MemOperand(ip), Operand(0, kRelocInfo_NONEPTR), r0);
StoreP(MemOperand(ip), Operand(0, RelocInfo::NONE), r0);
// Restore current context from top and clear it in debug mode.
mov(ip,
@ -1947,7 +1947,7 @@ void TurboAssembler::mov(Register dst, const Operand& src) {
value = src.immediate();
}
if (src.rmode() != kRelocInfo_NONEPTR) {
if (src.rmode() != RelocInfo::NONE) {
// some form of relocation needed
RecordRelocInfo(src.rmode(), value);
}
@ -3166,7 +3166,7 @@ void TurboAssembler::CmpP(Register src1, Register src2) {
// Compare 32-bit Register vs Immediate
// This helper will set up proper relocation entries if required.
void TurboAssembler::Cmp32(Register dst, const Operand& opnd) {
if (opnd.rmode() == kRelocInfo_NONEPTR) {
if (opnd.rmode() == RelocInfo::NONE) {
intptr_t value = opnd.immediate();
if (is_int16(value))
chi(dst, opnd);
@ -3183,7 +3183,7 @@ void TurboAssembler::Cmp32(Register dst, const Operand& opnd) {
// This helper will set up proper relocation entries if required.
void TurboAssembler::CmpP(Register dst, const Operand& opnd) {
#if V8_TARGET_ARCH_S390X
if (opnd.rmode() == kRelocInfo_NONEPTR) {
if (opnd.rmode() == RelocInfo::NONE) {
cgfi(dst, opnd);
} else {
mov(r0, opnd); // Need to generate 64-bit relocation
@ -3470,7 +3470,7 @@ void TurboAssembler::StoreP(Register src, const MemOperand& mem,
void TurboAssembler::StoreP(const MemOperand& mem, const Operand& opnd,
Register scratch) {
// Relocations not supported
DCHECK_EQ(opnd.rmode(), kRelocInfo_NONEPTR);
DCHECK_EQ(opnd.rmode(), RelocInfo::NONE);
// Try to use MVGHI/MVHI
if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT) && is_uint12(mem.offset()) &&

View File

@ -87,7 +87,7 @@ TEST(1) {
#endif
__ lr(r3, r2);
__ lhi(r2, Operand(0, kRelocInfo_NONEPTR));
__ lhi(r2, Operand(0, RelocInfo::NONE));
__ b(&C);
__ bind(&L);
@ -95,7 +95,7 @@ TEST(1) {
__ ahi(r3, Operand(-1 & 0xFFFF));
__ bind(&C);
__ cfi(r3, Operand(0, kRelocInfo_NONEPTR));
__ cfi(r3, Operand(0, RelocInfo::NONE));
__ bne(&L);
__ b(r14);
@ -137,7 +137,7 @@ TEST(2) {
__ ahi(r3, Operand(-1 & 0xFFFF));
__ bind(&C);
__ cfi(r3, Operand(0, kRelocInfo_NONEPTR));
__ cfi(r3, Operand(0, RelocInfo::NONE));
__ bne(&L);
__ b(r14);